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7.6
Operation
The DTC stores register information in on-chip RAM. When activated, the DTC reads register
information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated
register information back to on-chip RAM. The pre-storage of register information in memory
makes it possible to transfer data over any required number of channels. The transfer mode can be
specified as normal, repeat, or block transfer mode. Setting the CHNE bit in MRB to 1 makes it
possible to perform a number of transfers with a single activation source (chain transfer).
The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed depending on its register information.
Start
Read DTC vector
Read register information
Data transfer
Write register information
CHNE = 1
No
Transfer counter = 0
or DISEL = 1
No
Clear an activation flag
End
Figure 7.4 DTC Operation Flowchart
Section 7 Data Transfer Controller (DTC)
Next transfer
Yes
Yes
Clear DTCER
Interrupt exception
handling
Rev. 1.00 Mar. 12, 2008 Page 175 of 1178
REJ09B0403-0100
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