22.3.20 FIFO Clear Register (FCLR)
FCLR is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the
data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.
Do not clear a FIFO buffer during transfer.
Bit
Bit Name
7
6
EP3 CLR
5
EP1 CLR
4
EP2 CLR
3 to 1
0
EP0i CLR
Initial
Value
R/W
Description
Undefined
Reserved
The initial value should not be changed.
Undefined W
EP3 Clear
Writing 1 to this bit initializes the endpoint 3 transmit
FIFO buffer.
Undefined W
EP1 Clear
Writing 1 to this bit initializes both sides of the
endpoint 1 receive FIFO buffer.
Undefined W
EP2 Clear
Writing 1 to this bit initializes both sides of the
endpoint 2 transmit FIFO buffer.
All 0
R
Reserved
The initial value should not be changed.
Undefined W
EP0i Clear
Writing 1 to this bit initializes the endpoint 0 transmit
FIFO buffer.
Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 849 of 1178
REJ09B0403-0100