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Bit
Bit Name
2 to 0
CKS2 to
CKS0
Note:
* Only 0 can be written to clear the flag.
Initial
Value
R/W
Description
All 0
R/W
Clock Select 2 to 0
Select the clock source to be input to TCNT. The overflow
period for φ = 34 MHz is enclosed in parentheses.
000: φ/2 (period: 15.1 µs)
001: φ/64 (period: 481.9 µs)
010: φ/128 (period: 963.8 µs)
011: φ/512 (period: 3.856 ms)
100: φ/2048 (period: 15.42 ms)
101: φ/8192 (period: 61.68 ms)
110: φ/32768 (period: 246.7 ms)
111: φ/131072 (period: 986.9 ms)
Section 12 Watchdog Timer (WDT)
Rev. 1.00 Mar. 12, 2008 Page 417 of 1178
REJ09B0403-0100
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