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Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
21.2.1
E-DMAC Mode Register (EDMR)
EDMR is a 32-bit readable/writable register that specifies the operating mode of the E-DMAC.
The settings in this register are normally made in the initialization process following a reset. If the
EtherC and E-DMAC are initialized by means of this register during data transmission, abnormal
data may be sent onto the line. Operating mode settings must not be changed while the transmit
and receive functions are enabled. To change the operating mode, the EtherC and E-DMAC
modules are got into at their initial state by means of the software reset bit (SWR) in this register,
then make new settings. It takes 64 states to initialize the EtherC and E-DMAC. Therefore,
registers of the EtherC and E-DMAC should be accessed after 64 states have elapsed.
Bit
Bit Name
31 to 7
6
DE
5
DL1
4
DL0
3 to 1
Rev. 1.00 Mar. 12, 2008 Page 794 of 1178
REJ09B0403-0100
Initial
value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The initial value
should not be changed.
0
R/W
E-DMAC Data Endian Convert
Selects whether or not the endian format is converted
on data transfer by the E-DMAC. However, the
endian format of the descriptors and E-DMAC register
values are not converted regardless of this bit setting.
0: Endian format not converted (big endian)
1: Endian format converted (little endian)
0
R/W
Transmit/Receive Descriptor Length
0
R/W
These bits specify the transmit/receive descriptor
length.
00: 16 bytes
01: 32 bytes
10: 64 bytes
11: Setting prohibited
All 0
R
Reserved
These bits are always read as 0. The initial value
should not be changed.
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