Smic Interrupt Register 1 (Smicir1) - Renesas H8S Family Hardware Manual

19.3.24 SMIC Interrupt Register 1 (SMICIR1)

SMICIR1 is one of the registers used to implement SMIC mode. This register includes the bits that
enables/disables an interrupt to the slave. The IBFI3 interrupt is enabled by setting the IBFIE3 bit
in HICR2 to 1.
Bit Bit Name Initial Value Slave Host Description
7 to 5 
All 0
4 HDTWIE 0
3 HDTRIE 0
2 STARIE 0
1 CTLWIE 0
0 BUSYIE 0
R/W

R/W
Reserved
The initial value should not be changed.

R/W Transfer Data Transmission End Interrupt Enable
Enables or disables HDTWI interrupt that is IBFI3
interrupt source to the slave.
0: Disables transfer data transmission end interrupt
1: Enables transfer data transmission end interrupt

R/W Transfer Data Receive End Interrupt Enable
Enables or disables HDTRI interrupt that is IBFI3
interrupt source to the slave.
0: Disables transfer data receive end interrupt
1: Enables transfer data receive end interrupt

R/W Status Code Receive End Interrupt Enable
Enables or disables STARI interrupt that is IBFI3
interrupt source to the slave.
0: Disables status code receive end interrupt
1: Enables status code receive end interrupt

R/W Control Code Transmission End Interrupt Enable
Enables or disables CTLWI interrupt that is IBFI3
interrupt source to the slave.
0: Disables control code transmission end interrupt
1: Enables control code transmission end interrupt

R/W Transfer Start Interrupt Enable
Enables or disables BUSYI interrupt that is IBFI3
interrupt source to the slave.
0: Disables transfer start interrupt
1: Enables transfer start interrupt
Section 19 LPC Interface (LPC)
Rev. 1.00 Mar. 12, 2008 Page 717 of 1178
REJ09B0403-0100