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7.3
DTC Event Counter
To count events of EVENT 0 to EVENT15 by the DTC event counter function, set DTC as below.
Table 7.2
DTC Event Counter Conditions
Register
Bit
MRA
7, 6
5, 4
3, 2
1
0
MRB
7
6
5 to 0
SAR
23 to 0
DAR
23 to 0
CRAH
7 to 0
CRAL
7 to 0
CRBH
7 to 0
CRBL
7 to 0
DTCERC
4
KBCOMP
7
RAM
The corresponding flag to ECS input pin is set to 1 when the event pins that are specified by the
ECSB3 to ECSB0 in ECCR detect the edge events specified by the EDSB in ECCR. For this flag
state, status/address codes are generated.
An EVENTI interrupt request is generated even if only one bit in ECS is set to 1.
Bit Name
Description
SM1, SM0 00: SAR is fixed.
DM1, DM0 00: DAR is fixed.
MD1, MD0 01: Repeat mode
DTS
0: Destination is repeat area
Sz
1: Word size transfer
CHNE
0: Chain transfer is disabled
DISEL
0: Interrupt request is generated when data is transferred by
the number of specified times
B'000000
Identical optional RAM address. Its lower five bits are B'00000.
The start address of 16 words is this address. They are
incremented every time an event is detected in EVENT0 to
EVENT15.
H'FF
H'FF
H'FF
H'FF
DTCEC4
1: DTC function of the event counter is enabled
EVENTE
1: Event counter enable
(SAR, DAR) : Result of EVENT0 count
(SAR, DAR) + 2: Result of EVENT 1 count
(SAR, DAR) + 4: Result of EVENT 2 count
(SAR, DAR) + 30: Result of EVENT 15 count
Section 7 Data Transfer Controller (DTC)
↓
Rev. 1.00 Mar. 12, 2008 Page 169 of 1178
REJ09B0403-0100
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