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Figure 27.5 Note on Board Design of Oscillation Circuit Section............................................ 1056
Section 28 Power-Down Modes
Figure 28.1 Mode Transition Diagram ..................................................................................... 1065
Figure 28.2 Medium-Speed Mode Timing ............................................................................... 1068
Figure 28.3 Software Standby Mode Application Example ..................................................... 1070
Figure 28.4 Hardware Standby Mode Timing .......................................................................... 1071
Section 31 Electrical Characteristics
Figure 31.1 Darlington Transistor Drive Circuit (Example)..................................................... 1125
Figure 31.2 LED Drive Circuit (Example) ............................................................................... 1126
Figure 31.3 Output Load Circuit............................................................................................... 1127
Figure 31.4 System Clock Timing ............................................................................................ 1129
Figure 31.5 Oscillation Stabilization Timing............................................................................ 1129
Figure 31.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)..................... 1129
Figure 31.7 External Clock Input Timing................................................................................. 1130
Figure 31.8 Timing of External Clock Output Stabilization Delay Time ................................. 1130
Figure 31.9 Subclock Input Timing .......................................................................................... 1131
Figure 31.10 Reset Input Timing.............................................................................................. 1132
Figure 31.11 Interrupt Input Timing......................................................................................... 1133
Figure 31.12 Basic Bus Timing/2-State Access........................................................................ 1135
Figure 31.13 Basic Bus Timing/3-State Access........................................................................ 1136
Figure 31.14 Basic Bus Timing/3-State Access with One Wait State ...................................... 1137
Figure 31.15 Even Byte Access (ADMXE = 0) ....................................................................... 1138
Figure 31.16 Odd Byte Access (ADMXE = 0)......................................................................... 1139
Figure 31.17 Word Access (ADMXE = 0) ............................................................................... 1140
Figure 31.18 Burst ROM Access Timing/2-State Access......................................................... 1141
Figure 31.19 Burst ROM Access Timing/1-State Access......................................................... 1142
Figure 31.20 Multiplex Bus Timing/Data 2-State Access ........................................................ 1144
Figure 31.21 Multiplex Bus Timing/Data 3-State Access ........................................................ 1145
Figure 31.22 I/O Port Input/Output Timing.............................................................................. 1148
Figure 31.23 PWMX Output Timing........................................................................................ 1148
Figure 31.24 SCK Clock Input Timing..................................................................................... 1148
Figure 31.25 SCI Input/Output Timing (Clock Synchronous Mode) ....................................... 1148
Figure 31.26 A/D Converter External Trigger Input Timing.................................................... 1149
Figure 31.27 WDT Output Timing (RESO) ............................................................................. 1149
Figure 31.28 SSU Timing (Master, CPHS = 1) ........................................................................ 1149
Figure 31.29 SSU Timing (Master, CPHS = 0) ........................................................................ 1150
Figure 31.30 SSU Timing (Slave, CPHS = 1) .......................................................................... 1150
Figure 31.31 SSU Timing (Slave, CPHS = 0) .......................................................................... 1151
2
Figure 31.32 I
C Bus Interface Input/Output Timing ............................................................... 1153
Rev. 1.00 Mar. 12, 2008 Page xxxix of xIviii
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