Renesas H8S Family Hardware Manual page 643

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18.3.5 I C Bus Transfer Rate Select Register (IICX3)
IICX3 selects the IIC transfer rate clock and sets the transfer rate of IIC channel 3.
Bit Bit Name

7 to 4
3 TCSS
2 IICX5
1 IICX4
0 IICX3
Initial
Value R/W Description
 
Reserved
These bits cannot be modified. The read values are
undefined.
0 R/W Transfer Rate Clock Source Select
This bit selects a clock rate to be applied to the I
transfer rate.
0: φ/2
1: φ/4
0 R/W IIC Transfer Rate Select 5, 4, 3
0 R/W These bits are used to control IIC_5 to IIC_3 operation.
These bits select the transfer rate in master mode,
0 R/W
together with the CKS2 to CKS0 bits in ICMR. For the
transfer rate, see table 18.3.
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Section 18 I C Bus Interface (IIC)
Rev. 1.00 Mar. 12, 2008 Page 595 of 1178
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C bus
REJ09B0403-0100