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2
Section 18 I
C Bus Interface (IIC)
2
18.3.6
I
C Bus Control Register (ICCR)
2
ICCR controls the I
C bus interface and performs interrupt flag confirmation.
Bit
Bit Name
7
ICE
6
IEIC
5
MST
4
TRS
Rev. 1.00 Mar. 12, 2008 Page 598 of 1178
REJ09B0403-0100
Initial
Value
R/W
Description
2
0
R/W
I
C Bus Interface Enable
0: I
interface module internal state is initialized. SAR and
SARX can be accessed.
1: I
reception, they are connected to the SCL and SDA pins,
and the I
accessed.
2
0
R/W
I
C Bus Interface Interrupt Enable
0: Disables interrupts from the I
CPU.
1: Enables interrupts from the I
CPU.
0
R/W
Master/Slave Select
0
R/W
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode of the I
format. In slave receive mode with I
bit in the first frame immediately after the start condition
automatically sets these bits in receive mode or transmit
mode by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.
2
C bus interface modules are stopped and I
2
C bus interface modules can perform transfer and
2
C bus can be driven. ICMR and ICDR can be
2
C bus
2
C bus interface to the
2
C bus interface to the
2
C bus
2
C bus format, the R/W
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