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Section 13 Serial Communication Interface (SCI)
13.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit
Bit Name
7
TDRE
6
RDRF
Rev. 1.00 Mar. 12, 2008 Page 440 of 1178
REJ09B0403-0100
Initial
Value
R/W
Description
1
R/(W)* Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
0
R/(W)* Receive Data Register Full
Indicates that receive data is stored in RDR.
[Setting condition]
•
[Clearing conditions]
•
•
The RDRF flag is not affected and retains its previous value
when the RE bit in SCR is cleared to 0.
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and TDR is
ready for data write
When 0 is written to TDRE after reading TDRE = 1
When a TXI interrupt request is issued allowing DTC to
write data to TDR
When serial reception ends normally and receive data is
transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF = 1
When an RXI interrupt request is issued allowing DTC to
read data from RDR
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