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Section 8 I/O Ports
(4)
Noise Canceler Enable Register (P3NCE)
P3NCE enables or disables the noise canceler circuit at port 3.
Bit
Bit Name
7
P37NCE
6
P36NCE
5
P35NCE
4
P34NCE
3
P33NCE
2
P32NCE
1
P31NCE
0
P30NCE
(5)
Noise Canceler Mode Control Register (P3NCMC)
When the noise canceler is enabled, P3NCMC controls whether 1 or 0 is expected for the input
signal to port 3 in bit units.
Bit
Bit Name
7
P37NCMC
6
P36NCMC
5
P35NCMC
4
P34NCMC
3
P33NCMC
2
P32NCMC
1
P31NCMC
0
P30NCMC
Rev. 1.00 Mar. 12, 2008 Page 202 of 1178
REJ09B0403-0100
Initial Value
R/W Description
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial Value
R/W Description
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
•
Normal extended mode (ADMXE = 0)
The pins function as bidirectional data bus pins. Set
this register to 0.
•
Other modes
Enables the noise canceler circuit for the
corresponding pin and the pin state is fetched into
P3DR at the sampling cycle set by NCCS.
The operation changes according to the other
control bits.
•
Normal extended mode (ADMXE = 0)
This register has no effect on operation.
•
Other modes
1 expected: 1 is stored in the port data register
while 1 is input stably.
0 expected: 0 is stored in the port data register
while 0 is input stably.
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