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Bit
Bit Name
5
MST
4
TRS
3
ACKE
Initial
Value
R/W
Description
0
R/W
[MST clearing conditions]
0
R/W
(1) When 0 is written by software
(2) When lost in bus contention in I
[MST setting conditions]
(1) When 1 is written by software (for MST clearing
(2) When 1 is written in MST after reading MST = 0 (for
[TRS clearing conditions]
(1) When 0 is written by software (except for TRS setting
(2) When 0 is written in TRS after reading TRS = 1 (for
(3) When lost in bus contention in I
[TRS setting conditions]
(1) When 1 is written by software (except for TRS clearing
(2) When 1 is written in TRS after reading TRS = 0 (for
(3) When 1 is received as the R/W bit after the first frame
0
R/W
Acknowledge Bit Decision Selection
0: The value of the acknowledge bit is ignored, and
1: If the acknowledge bit is 1, continuous transfer is
Depending on the receiving device, the acknowledge bit
may be significant, in indicating completion of processing
of the received data, for instance, or may be fixed at 1 and
have no significance.
mode
condition 1)
MST clearing condition 2)
condition 3)
TRS setting condition 3)
mode
condition 3)
TRS clearing condition 3)
address matching in I
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the ACKB
bit in ICSR, which is always 0.
halted.
Rev. 1.00 Mar. 12, 2008 Page 599 of 1178
2
Section 18 I
C Bus Interface (IIC)
2
C bus format master
2
C bus format master
2
C bus format slave mode
REJ09B0403-0100
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