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LCLK
LFRAME
LAD3 to
LAD0
Number of clocks
LCLK
LFRAME
LAD3 to LAD0
19.4.3
SMIC Mode Transfer Flow
Figure 19.4 shows the write transfer flow and figure 19.5 shows the read transfer flow in SMIC
mode.
Start
ADDR
Cycle type,
direction,
and size
1
1
4
Figure 19.2 Typical LFRAME Timing
Start
ADDR
Cycle type,
direction,
and size
Figure 19.3 Abort Mechanism
TAR
Sync
Data
2
1
2
TAR
Sync
Slave must stop driving
Too many Syncs
cause timeout
Rev. 1.00 Mar. 12, 2008 Page 735 of 1178
Section 19 LPC Interface (LPC)
TAR
Start
2
1
Master will
drive high
REJ09B0403-0100
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