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Section 12 Watchdog Timer (WDT)
• TCSR_1
Bit
Bit Name
7
OVF
6
WT/IT
5
TME
4
PSS
3
RST/NMI
Rev. 1.00 Mar. 12, 2008 Page 418 of 1178
REJ09B0403-0100
Initial
Value
R/W
Description
1
0
R/(W)*
Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting conditions]
•
•
[Clearing conditions]
•
•
0
R/W
Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
0
R/W
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
0
R/W
Prescaler Select
Selects the clock source to be input to TCNT.
0: Counts the divided cycle of φ–based prescaler (PSM)
1: Counts the divided cycle of φSUB–based prescaler
(PSS)
0
R/W
Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by
the internal reset.
When TCSR is read when OVF = 1*
to OVF
When 0 is written to TME
2
, then 0 is written
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