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Figure 13.1 is a block diagram of SCI_1 and SCI_3.
RxD1/RxD3
TxD1/TxD3
SCK1/SCK3
[Legend]
RSR:
RDR:
TSR:
TDR:
SMR:
Module data bus
RDR
TDR
RSR
TSR
Parity generation
Parity check
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Figure 13.1 Block Diagram of SCI_1 and SCI_3
Section 13 Serial Communication Interface (SCI)
SCMR
SSR
SCR
Baud rate
generator
SMR
Transmission/
reception control
Clock
External clock
SCR:
Serial control register
SSR:
Serial status register
SCMR: Smart card mode register
BRR:
Bit rate register
Rev. 1.00 Mar. 12, 2008 Page 431 of 1178
BRR
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
REJ09B0403-0100
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