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(5)
Noise Canceler Mode Control Register (P4BNCMC)
P4BNCMC controls whether 1 or 0 is expected for the input signal to port 4 in bit units.
Bit
Bit Name
7
P47NCMC
6
P46NCMC
5
P45NCMC
4
P44NCMC
3 to 0 PB3NCMC
to
PB0NCMC
(6)
Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit
Bit Name
7 to 3
2
NCCK2
1
NCCK1
0
NCCK0
Initial Value
R/W Description
1
R/W
1
R/W
1
R/W
1
R/W
All 1
R/W Bits for port B setting
Initial Value
R/W
Undefined
R/W
0
R/W
0
R/W
0
R/W
Expected value setting
1 expected: 1 is stored in the port data register while 1
is input stably
0 expected: 0 is stored in the port data register while 0
is input stably
Description
Reserved
Undefined value is read from these bits.
These bits set the sampling cycle of the noise
cancelers.
•
When φ = 34 MHz
000: 0.06 µs
φ/2
001: 0.94 µs
φ/32
010: 15.1 µs
φ/512
011: 240.9 µs φ/8192
Rev. 1.00 Mar. 12, 2008 Page 209 of 1178
Section 8 I/O Ports
100: 963.8 µs φ/32768
φ/65536
101: 1.9 ms
φ/131072
110: 3.9 ms
φ/262144
111: 7.7 ms
REJ09B0403-0100
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