Endpoint Stall Register (Epstl) - Renesas H8S Family Hardware Manual

22.3.22 Endpoint Stall Register (EPSTL)

The bits in EPSTL are used to forcibly stall the endpoints on the application side. While a bit is set
to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for endpoint 0
is cleared automatically on reception of 8-byte command data for which decoding is performed by
the function and the EP0 STL bit is cleared. When the SETUPTS flag in the IFR0 register is set to
1, writing 1 to the EP0 STL bit is ignored. For detailed operation, see section 22.7, Stall
Operations.
Bit Bit Name

7 to 4
3 EP3STL
2 EP2STL
1 EP1STL
0 EP0STL
Initial
Value
R/W Description
Reserved
All 0 R
These bits are always read as 0. The initial value
should not be changed.
0 R/W EP3 Stall
When this bit is set to 1, endpoint 3 is placed in the
stall state.
0 R/W EP2 Stall
When this bit is set to 1, endpoint 2 is placed in the
stall state.
0 R/W EP1 Stall
When this bit is set to 1, endpoint 1 is placed in the
stall state.
0 R/W EP0 Stall
When this bit is set to 1, endpoint 0 is placed in the
stall state.
Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 853 of 1178
REJ09B0403-0100