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φ
RES
Internal address bus
Internal read signal
Internal write signal
Internal data bus
(1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2)U + (2)L)
(4) First program instruction
4.3.2
Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
On-Chip Peripheral Modules after Reset is Cancelled
After a reset is cancelled, the module stop control registers (MSTPCR, MSTPCRA, SUBMSTPB,
and SUBMSTPA) are initialized, and all modules except the DTC operate in module stop mode.
Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read
from and write to these registers, clear module stop mode.
Vector
fetch
(1) U
(2)
U
Figure 4.1 Reset Sequence
Section 4 Exception Handling
Internal
Prefetch of first
processing
program instruction
(1) L
High
(2)
L
Rev. 1.00 Mar. 12, 2008 Page 73 of 1178
(3)
(4)
REJ09B0403-0100
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