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11.2.1 Timer Counter (TCNT)......................................................................................... 394
11.2.2 Time Constant Register A (TCORA).................................................................... 395
11.2.3 Time Constant Register B (TCORB) .................................................................... 395
11.2.4 Timer Control Register (TCR).............................................................................. 396
11.2.5 Timer Control/Status Register (TCSR)................................................................. 399
11.2.6 Timer Connection Register S (TCONRS)............................................................. 403
11.3 Operation Timing............................................................................................................... 404
11.3.1 TCNT Count Timing ............................................................................................ 404
11.3.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 404
11.3.3 Timing of Counter Clear at Compare-Match ........................................................ 405
11.3.4 Timing of Overflow Flag (OVF) Setting .............................................................. 405
11.4 TMR_0 and TMR_1 Cascaded Connection ....................................................................... 406
11.4.1 16-Bit Count Mode ............................................................................................... 406
11.4.2 Compare-Match Count Mode ............................................................................... 406
11.5 Interrupt Sources................................................................................................................ 407
11.6 Usage Notes ....................................................................................................................... 408
11.6.1 Conflict between TCNT Write and Counter Clear................................................ 408
11.6.2 Conflict between TCNT Write and Increment...................................................... 409
11.6.3 Conflict between TCOR Write and Compare-Match............................................ 410
11.6.4 Switching of Internal Clocks and TCNT Operation.............................................. 411
11.6.5 Mode Setting with Cascaded Connection ............................................................. 412
Section 12 Watchdog Timer (Wdt)..................................................................413
12.1 Features.............................................................................................................................. 413
12.2 Input/Output Pins ............................................................................................................... 415
12.3 Register Descriptions ......................................................................................................... 415
12.3.1 Timer Counter (TCNT)......................................................................................... 415
12.3.2 Timer Control/Status Register (TCSR)................................................................. 416
12.4 Operation ........................................................................................................................... 420
12.4.1 Watchdog Timer Mode ......................................................................................... 420
12.4.2 Interval Timer Mode............................................................................................. 422
12.4.3 RESO Signal Output Timing ................................................................................ 423
12.5 Interrupt Sources................................................................................................................ 424
12.6 Usage Notes ....................................................................................................................... 425
12.6.1 Notes on Register Access...................................................................................... 425
12.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 426
12.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 426
12.6.4 Changing Value of PSS Bit................................................................................... 426
12.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode................. 427
12.6.6 System Reset by RESO Signal ............................................................................. 427
Rev. 1.00 Mar. 12, 2008 Page xv of xIviii
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