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Section 6 Bus Controller (BSC)
(4)
16-Bit, 3-State Access Space
Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access
space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the
lower half (D7 to D0) for odd addresses. Wait states can be inserted.
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS (IOSE = 0)
*
D15 to D8
Read
D7 to D0
Write
D15 to D8
D7 to D0
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)
Rev. 1.00 Mar. 12, 2008 Page 134 of 1178
REJ09B0403-0100
T
1
φ
RD
HWR
LWR
Bus cycle
T
T
2
3
High level
Valid
Undefined
Valid
Invalid
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