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Timer Interrupt Enable Register (Tier) - Renesas H8S Family Hardware Manual

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10.2.4

Timer Interrupt Enable Register (TIER)

TIER enables and disables interrupt requests.
Bit
Bit Name
7 to 4
3
OCIAE
2
OCIBE
1
OVIE
0
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
0
R/W
Output Compare Interrupt A Enable
Selects whether to enable output compare interrupt A
request (OCIA) when output compare flag A (OCFA) in
TCSR is set to 1.
0: OCIA requested by OCFA is disabled
1: OCIA requested by OCFA is enabled
0
R/W
Output Compare Interrupt B Enable
Selects whether to enable output compare interrupt B
request (OCIB) when output compare flag B (OCFB) in
TCSR is set to 1.
0: OCIB requested by OCFB is disabled
1: OCIB requested by OCFB is enabled
0
R/W
Timer Overflow Interrupt Enable
Selects whether to enable a free-running timer overflow
request interrupt (FOVI) when the timer overflow flag
(OVF) in TCSR is set to 1.
0: FOVI requested by OVF is disabled
1: FOVI requested by OVF is enabled
0
R
Reserved
This bit is always read as 0 and cannot be modified.
Section 10 16-Bit Free-Running Timer (FRT)
Rev. 1.00 Mar. 12, 2008 Page 377 of 1178
REJ09B0403-0100

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