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2
Section 18 I
C Bus Interface (IIC)
Master transmit mode
SCL
9
(master output)
SDA
A
(slave output)
SDA
(master output)
IRIC
IRTR
ICDRF
ICDRR
User processing
Figure 18.11 Master Receive Mode Operation Timing Example
SCL
7
8
(master output)
SDA
Bit 1
Bit 0
(slave output)
Data 2
SDA
(master output)
IRIC
IRTR
ICDRF
ICDRR
Data 1
[4] IRIC clear
User processing
Figure 18.12 Stop Condition Issuance Timing Example in Master Receive Mode
Rev. 1.00 Mar. 12, 2008 Page 626 of 1178
REJ09B0403-0100
Master receive mode
SCL is fixed low until ICDR is read
1
2
3
Bit 7
Bit 6
Bit 5
Data 1
[1] TRS cleared to 0
[2] ICDR read
[1] IRIC clear
(MLS = WAIT = 0, HNDS = 1)
SCL is fixed low until ICDR is read
9
1
2
Bit 7
Bit 6
[3]
A
[7] ICDR read
(Data 2)
[6] ACKB set to 1
(MLS = WAIT = 0, HNDS = 1)
4
5
6
7
8
Bit 2
Bit 0
Bit 4
Bit 3
Bit 1
Undefined value
[4] IRIC clear
(Dummy read)
SCL is fixed low until ICDR is read
3
4
5
6
7
Bit 2
Bit 5
Bit 4
Bit 3
Bit 1
Data 3
Data 2
[9] IRIC clear
SCL is fixed low until ICDR is read
9
1
2
Bit 6
Bit 7
[3]
Data 2
A
Data 1
[6] ICDR read
(Data 1)
Stop condition generation
8
9
Bit 0
[8]
A
Data 3
[10] ICDR read
(Data 3)
[11] BBSY cleared to 0 and
SCP cleared to 0
(Stop condition instruction issuance)
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