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Figure 13.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
Synchronization
clock
Serial data
TDRE
TEND
TXI interrupt
request generated
Figure 13.16 Sample SCI Transmission Operation in Clock Synchronous Mode
Transfer direction
Bit 0
Bit 1
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
service routine
1 frame
Section 13 Serial Communication Interface (SCI)
Bit 7
Bit 0
Bit 1
TXI interrupt
request generated
Rev. 1.00 Mar. 12, 2008 Page 469 of 1178
Bit 6
Bit 7
TEI interrupt request
generated
REJ09B0403-0100
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