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Section 17 Synchronous Serial Communication Unit (SSU)
17.3.2
SS Control Register L (SSCRL)
SSCRL selects operating mode, software reset, and transmit/receive data length.
Bit
Bit Name
7
6
SSUMS
5
SRES
4 to 2
1
DATS1
0
DATS0
Rev. 1.00 Mar. 12, 2008 Page 556 of 1178
REJ09B0403-0100
Initial
Value
R/W
0
R/W
0
R/W
0
R/W
All 0
R/W
0
R/W
0
R/W
Description
Reserved
This bit is always read as 0. The initial value should not
be changed.
Selects transfer mode from SSU mode and clock
synchronous mode.
0: SSU mode
1: Clock synchronous mode
Software Reset
Setting this bit to 1 forcibly resets the SSU internal
sequencer. After that, this bit is automatically cleared.
The ORER, TEND, TDRE, RDRF, and CE bits in SSSR
and the TE and RE bits in SSER are also initialized.
Values of other bits for SSU registers are held.
To stop transfer, set this bit to 1 to reset the SSU
internal sequencer.
Reserved
These bits are always read as 0. The initial value
should not be changed.
Transmit/Receive Data Length Select
Select serial data length.
00: 8 bits
01: 16 bits
10: 32 bits
11: Setting prohibited
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