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Renesas H8S Family Hardware Manual page 985

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Table 25.4 Parameters and Target Modes
Name of
Abbrevia-
Parameter
tion
Download pass/fail
DPFR
result
Flash pass/fail
FPFR
result
Flash
FPEFEQ
programming/
erasing frequency
control
Flash multipurpose
FMPAR
address area
Flash multipurpose
FMPDR
data destination
area
Flash erase block
FEBS
select
Note:
* A single byte of the start address to download an on-chip program, which is specified by
FTDAR
Down
Initializa-
Program-
Load
tion
ming
Section 25 Flash Memory
Initial
Erasure
R/W
Value
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
Rev. 1.00 Mar. 12, 2008 Page 937 of 1178
Alloca-
tion
On-chip
RAM*
R0L of
CPU
ER0 of
CPU
ER1 of
CPU
ER0 of
CPU
R0L of
CPU
REJ09B0403-0100

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