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Renesas H8S Family Hardware Manual page 315

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(2)
Port F Output Data Register (PFODR)
PFODR stores output data for the port F pins. PEODR is initialized only by a system reset, and
retains the value even if an internal reset signal of the WDT is generated.
Bit
Bit Name
7
6
PF6ODR
5
PF5ODR
4
PF4ODR
3
PF3ODR
2
PF2ODR
1
PF1ODR
0
PF0ODR
(3)
Port F Input Data Register (PFPIN)
PFPIN indicates the pin states of port F.
Bit
Bit Name
7
6
PF6PIN
5
PF5PIN
4
PF4PIN
3
PF3PIN
2
PF2PIN
1
PF1PIN
0
PF0PIN
Note: The initial value of these pins is determined in accordance with the state of pins PF6 to
PF0.
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial Value
R/W
Undefined*
R
Undefined*
R
Undefined*
R
Undefined*
R
Undefined*
R
Undefined*
R
Undefined*
R
Description
Reserved
Undefined value is read from this bit.
Stores the output data for the pin that is used as the
general output port.
Description
Reserved
Undefined value is read from this bit.
When this register is read, the pin states are read.
Since this register is allocated to the same address as
PFDDR, writing to this register writes data to PFDDR
and the port F setting is changed.
Rev. 1.00 Mar. 12, 2008 Page 267 of 1178
Section 8 I/O Ports
REJ09B0403-0100

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