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Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
IRQ0
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
Rev. 1.00 Mar. 12, 2008 Page 94 of 1178
REJ09B0403-0100
Program execution state
Interrupt generated?
Yes
An interrupt with interrupt
control level 1?
Yes
No
No
Yes
IRQ1
Yes
EINT
Yes
Save PC and CCR
Read vector address
Branch to interrupt handling routine
No
Yes
NMI
No
No
No
IRQ0
Yes
IRQ1
Yes
No
I = 0
Yes
I
1
Pending
No
EINT
Yes
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