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2
Section 18 I
C Bus Interface (IIC)
12. Clear the IRIC flag to 0.
Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP
in ICCR. This changes SDA from low to high when SCL is high, and generates the stop
condition.
Start condition generation
SCL
(master output)
SDA
(master output)
SDA
(slave output)
ICDRE
IRIC
IRTR
ICDRT
ICDRS
Note: Do not set ICDR
during this period.
[4] BBSY set to 1 and
User processing
SCP cleared to 0
(start condition issuance)
Figure 18.8 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)
Rev. 1.00 Mar. 12, 2008 Page 622 of 1178
REJ09B0403-0100
1
2
Bit 7
Bit 6
[5]
Interrupt
request
Address + R/W
Address + R/W
[6] ICDR write
3
4
5
6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Slave address
[6] IRIC clear
7
8
9
Bit 0
R/W
[7]
A
Interrupt
request
Data 1
[9] ICDR write
[9] IRIC clear
1
2
Bit 7
Bit 6
Data 1
Data 1
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