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13.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 13.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clock synchronous mode, and smart card interface mode. The initial value of BRR is H
can be read from or written to by the CPU at all times.
Table 13.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Asynchronous mode
Clock synchronous mode
Smart card interface mode
[Legend]
B:
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
N:
φ:
Operating frequency (MHz)
n and S:
Determined by the SMR settings shown in the following table.
SMR Setting
CKS1
0
0
1
1
Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the
maximum bit rate settable for each frequency. Table 13.6 and 13.8 show sample N settings in
BRR in clock synchronous mode and smart card interface mode, respectively. In smart card
interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected.
For details, see section 13.7.4, Receive Data Sampling Timing and Reception Margin. Tables 13.5
and 13.7 show the maximum bit rates with external clock input.
Bit Rate
φ × 10
B =
2n – 1
64 × 2
φ × 10
B =
2n – 1
8 × 2
φ × 10
B =
2n + 1
S × 2
CKS0
n
0
0
1
1
0
2
1
3
Section 13 Serial Communication Interface (SCI)
Error
6
Error (%) = {
× (N + 1)
6
× (N + 1)
6
Error (%) =
× (N + 1)
BCP1
0
0
1
1
Rev. 1.00 Mar. 12, 2008 Page 445 of 1178
'
φ × 10
6
2n – 1
B × 64 × 2
× (N + 1)
φ × 10
6
{
2n + 1
B × S × 2
× (N + 1)
SMR Setting
BCP0
0
1
0
1
REJ09B0403-0100
FF, and it
– 1 } × 100
}
–1 × 100
S
32
64
372
256
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