Address Break Control Register (Abrkcr) - Renesas H8S Family Hardware Manual

Section 5 Interrupt Controller
Table 5.2 Correspondence between Interrupt Source and ICR
Bit Bit Name ICRA
7 ICRn7 IRQ0
6 ICRn6 IRQ1
5 ICRn5 IRQ2, IRQ3
4 ICRn4 IRQ4, IRQ5
3 ICRn3 IRQ6, IRQ7
2 ICRn2 DTC
1 ICRn1 WDT_0
0 ICRn0 WDT_1
[Legend]
n: A to D
:
Reserved. The write value should always be 0.
5.3.2

Address Break Control Register (ABRKCR)

ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an
address break is requested.
Initial
Bit Bit Name Value
7 CMF Undefined R
6 to 1 — All 0
0 BIE 0
Rev. 1.00 Mar. 12, 2008 Page 80 of 1178
REJ09B0403-0100
ICRB
A/D converter
FRT
—
TMR_X
TMR_0
TMR_1
TMR_Y
IIC_4, IIC_5
R/W Description
Condition Match Flag
Address break source flag. Indicates that an address
specified by BARA to BARC is prefetched.
[Clearing condition]
When an exception handling is executed for an address
break interrupt.
[Setting condition]
When an address specified by BARA to BARC is
prefetched while the BIE flag is set to 1.
R Reserved
These bits are always read as 0 and cannot be modified.
R/W Break Interrupt Enable
Enables or disables address break.
0: Disabled
1: Enabled
Register
ICRC
SCI_3
SCI_1
SSU
IIC_0
IIC_1
IIC_2, IIC_3
LPC
USB (only in the
H8S/2472)
ICRD
IRQ8 to IRQ11
IRQ12 to IRQ15
EtherC
—
—
PECI
SCIF
—