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Table Of Contents - Renesas H8S Family Hardware Manual

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21.3.1 Descriptor List and Data Buffers .......................................................................... 816
21.3.2 Transmission......................................................................................................... 826
21.3.3 Reception .............................................................................................................. 828
21.3.4 Multi-Buffer Frame Transmit/Receive Processing ............................................... 830
Section 22 Usb Function Module (Usb)..........................................................833
22.1 Features.............................................................................................................................. 833
22.2 Input/Output Pins ............................................................................................................... 834
22.3 Register Descriptions ......................................................................................................... 835
22.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 836
22.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 838
22.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 839
22.3.4 Interrupt Select Register 0 (ISR0)......................................................................... 840
22.3.5 Interrupt Select Register 1 (ISR1)......................................................................... 841
22.3.6 Interrupt Select Register 2 (ISR2)......................................................................... 841
22.3.7 Interrupt Enable Register 0 (IER0) ....................................................................... 842
22.3.8 Interrupt Enable Register 1 (IER1) ....................................................................... 842
22.3.9 Interrupt Enable Register 2 (IER2) ....................................................................... 843
22.3.10 EP0i Data Register (EPDR0i)............................................................................... 843
22.3.11 EP0o Data Register (EPDR0o) ............................................................................. 844
22.3.12 EP0s Data Register (EPDR0s) .............................................................................. 844
22.3.13 EP1 Data Register (EPDR1) ................................................................................. 845
22.3.14 EP2 Data Register (EPDR2) ................................................................................. 845
22.3.15 EP3 Data Register (EPDR3) ................................................................................. 845
22.3.16 EP0o Receive Data Size Register (EPSZ0o) ........................................................ 846
22.3.17 EP1 Receive Data Size Register (EPSZ1) ............................................................ 846
22.3.18 Trigger Register (TRG)......................................................................................... 846
22.3.19 Data Status Register (DASTS).............................................................................. 848
22.3.20 FIFO Clear Register (FCLR) ................................................................................ 849
22.3.21 DTC Transfer Setting Register (DMA) ................................................................ 850
22.3.22 Endpoint Stall Register (EPSTL).......................................................................... 853
22.3.23 Configuration Value Register (CVR) ................................................................... 854
22.3.24 Control Register (CTLR) ...................................................................................... 854
22.3.25 Endpoint Information Register (EPIR) ................................................................. 856
22.3.26 Transceiver Test Register 0 (TRNTREG0)........................................................... 860
22.3.27 Transceiver Test Register 1 (TRNTREG1)........................................................... 861
22.4 Interrupt Sources................................................................................................................ 863
22.5 Operation ........................................................................................................................... 865
22.5.1 Operation at Cable Connection ............................................................................. 865
22.5.2 Operation at Cable Disconnection ........................................................................ 866
Rev. 1.00 Mar. 12, 2008 Page xxiii of xIviii

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R4f2472R4f2462H8s/2462H8s/2400 seriesH8s/2472