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Section 1 Overview
Table 1.1
Pin Assignments in Each Operating Mode ............................................................... 6
Table 1.2
Pin Functions .......................................................................................................... 13
Section 2 CPU
Table 2.1
Instruction Classification ........................................................................................ 39
Table 2.2
Operation Notation ................................................................................................. 40
Table 2.3
Data Transfer Instructions....................................................................................... 41
Table 2.4
Arithmetic Operations Instructions (1) ................................................................... 42
Table 2.4
Arithmetic Operations Instructions (2) ................................................................... 43
Table 2.5
Logic Operations Instructions................................................................................. 44
Table 2.6
Shift Instructions..................................................................................................... 44
Table 2.7
Bit Manipulation Instructions (1)............................................................................ 45
Table 2.7
Bit Manipulation Instructions (2)............................................................................ 46
Table 2.8
Branch Instructions ................................................................................................. 47
Table 2.9
System Control Instructions.................................................................................... 48
Table 2.10
Block Data Transfer Instructions ............................................................................ 49
Table 2.11
Addressing Modes .................................................................................................. 51
Table 2.12
Absolute Address Access Ranges ........................................................................... 53
Table 2.13
Effective Address Calculation (1)........................................................................... 55
Table 2.13
Effective Address Calculation (2)........................................................................... 56
Section 3 MCU Operating Modes
Table 3.1
MCU Operating Mode Selection ............................................................................ 61
Section 4 Exception Handling
Table 4.1
Exception Types and Priority.................................................................................. 69
Table 4.2
Exception Handling Vector Table........................................................................... 70
Table 4.3
Status of CCR after Trap Instruction Exception Handling ..................................... 74
Section 5 Interrupt Controller
Table 5.1
Pin Configuration.................................................................................................... 78
Table 5.2
Correspondence between Interrupt Source and ICR ............................................... 80
Table 5.3
Interrupt Sources, Vector Addresses, and Interrupt Priorities................................. 88
Table 5.4
Interrupt Control Modes ......................................................................................... 91
Table 5.5
Interrupts Selected in Each Interrupt Control Mode ............................................... 92
Table 5.6
Operations and Control Signal Functions in Each Interrupt Control Mode............ 93
Table 5.7
Interrupt Response Times ....................................................................................... 99
Table 5.8
Number of States in Interrupt Handling Routine Execution Status ........................ 99
Tables
Rev. 1.00 Mar. 12, 2008 Page xli of xIviii
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