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1.2
Block Diagram
Clock pulse
DTC
generator
EtherC
E-DMAC
EVC
SCI_1, SCI_3
SSU
FRT
IIC_0 to IIC_5
[Legend]
CPU:
Central processing unit
DTC:
Data transfer controller
EVC:
Event counter
SCI:
Serial communication interface
SCIF:
Serial communication interface with FIFO
2
IIC:
I
C bus interface
EtherC:
Ethernet controller
E-DMAC: Direct memory access controller for Ethernet controller
SSU:
Synchronous serial communication unit
USB:
USB function module
FRT:
16-bit free running timer
PWM:
14-bit PWM timer
LPC:
LPC interface
WDT:
Watchdog timer
JTAG:
Boundary scan
PECI:
PECI interface
Figure 1.1 Internal Block Diagram
ROM
H8S/2600
RAM
(Flash)
CPU
40K
512K
(+16K UB)
LPC
WDT × 2
14-bit PWM × 4
A/D converter
8-bit timer × 4
USB
(only in the H8S/2472)
PECI
Rev. 1.00 Mar. 12, 2008 Page 3 of 1178
Section 1 Overview
REJ09B0403-0100
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