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16.3
Register Descriptions
Two registers are provided for serial pin multiplexed modes. Serial multiplexed mode register 0
(SMR0) enables or disables the serial pin multiplexing function, selects a serial pin multiplexed
mode out of 5 modes, and provides bits for port monitoring. Serial multiplexed mode register 1
(SMR1) provides bits for port monitoring and controls outputs on the relevant port pins.
• Serial multiplexed mode register 0 (SMR0)
• Serial multiplexed mode register 1 (SMR1)
16.3.1
Serial Multiplexed Mode Register 0 (SMR0)
Bit
Initial
Name
Value
Bit
7
DCD1
6
RI1
5
DSR1
4
SME
0
3
0
2
SM2
0
1
SM1
0
0
SM0
0
R/W
Description
Monitors the state of the DCD line in modes 1, 3, and
R
4.
Monitors the state of the RI line in modes 1, 3, and 4.
R
Monitors the state of the DSR line in modes 1, 3, and
R
4.
R/W
Serial Pin Multiplex Enable
0: Pin multiplexing disabled
1: Pin multiplexing enabled
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W
Serial Pin Multiplexed Mode Select
R/W
These bits select a serial pin multiplexed mode. This
selection is only enabled when SME bit is 1.
R/W
000: Serial multiplexed mode 0
001: Serial multiplexed mode 1
010: Serial multiplexed mode 2
011: Serial multiplexed mode 3
100: Serial multiplexed mode 4
101: Reserved (Do not modify)
110: Reserved (Do not modify)
111: Reserved (Do not modify)
Section 16 Serial Pin Multiplexed Modes
Rev. 1.00 Mar. 12, 2008 Page 543 of 1178
REJ09B0403-0100
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