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Bit
Bit Name
4
3
FLSHE
2
—
1
ICKS1
0
ICKS0
Initial
Value
R/W
Description
0
R/W
Reserved
The initial value should not be changed.
0
R/W
Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FCCS, FPCS, FECS, FKEY, FMATS, FTDAR),
control registers of power-down states (SBYCR,
LPWRCR, MSTPCRH, MSTPCRL), and control registers
of on-chip peripheral modules (BCR2, WSCR2, PCSR,
SYSCR2).
0: Area from H'FFFE88 to H'FFFE8F is reserved. Control
registers of power-down states and on-chip peripheral
modules are accessed in an area from H'FFFF80 to
H'FFFF87.
1: Control registers of flash memory are accessed in an
area from H'FFFE88 to H'FFFE8F.
Area from H'FFFF80 to H'FFFF87 is reserved.
1
R/(W)
Reserved
The initial value should not be changed.
0
R/W
Internal Clock Source Select 1, 0
0
R/W
These bits select a clock to be input to the timer counter
(TCNT) and a count condition together with bits CKS2 to
CKS0 in the timer control register (TCR). For details, see
section 11.2.4, Timer Control Register (TCR).
Section 3 MCU Operating Modes
Rev. 1.00 Mar. 12, 2008 Page 65 of 1178
REJ09B0403-0100
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