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SDA
8
9
SCL
Data
TRS
transmission
TRS bit setting
The rise of the 9th clock is detected
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
13. Note on ICDR read in transmit mode and ICDR write in receive mode
When ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS =
0), the SCL pin may not be held low in some cases after transmit/receive operation has been
completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before
ICDR is accessed correctly. To access ICDR correctly, read the ICDR after setting receive
mode or write to the ICDR after setting transmit mode.
Restart condition
(a)
1
Address reception
TRS bit setting is suspended in this period
ICDR dummy read
Figure 18.34 TRS Bit Set Timing in Slave Mode
(b)
2
3
4
5
6
Rev. 1.00 Mar. 12, 2008 Page 661 of 1178
2
Section 18 I
C Bus Interface (IIC)
A
7
8
9
The rise of the 9th clock is detected
REJ09B0403-0100
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