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Section 22 USB Function Module (USB)
Bit
Bit Name
0
EP1DMAE
Rev. 1.00 Mar. 12, 2008 Page 852 of 1178
REJ09B0403-0100
Initial
Value
R/W
Description
0
R/W
Endpoint 1 DTC Transfer Enable
When this bit is set, the DTC start interrupt signal
(USBINTN0) is asserted and DTC transfer is enabled
from the endpoint 1 receive FIFO buffer to memory. If
there is at least one byte of receive data in the FIFO
buffer, the DTC start interrupt signal (USBINTN0) is
asserted. In DTC transfer, when all the received data
is read, EP1 is automatically read and the completion
trigger operates.
EP1-related interrupt requests to the CPU are not
automatically masked.
•
1. Set the number of transfers in the DTC.
2. Set the DTC to be activated by USBINTN0.
3. Write 1 to this bit.
4. Activate the DTC.
5. DTC transfer is performed.
6. DTC transfer end interrupt is generated.
7. Write 0 to the EP2DMAE bit in DMA.
8. Write 0 to the EP2EMPTY bit in IFR0.
See section 22.8.2, DTC Transfer for Endpoint 1.
Operating procedure:
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