Page 1 REJ09B0104-0300 H8SX/1520 Group Hardware Manual Renesas 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series H8SX/1527 R5F61527 H8SX/1525 R5F61525 Rev.3.00 Revision Date: Mar. 14, 2006 Downloaded from Elcodis.com electronic components distributor...
Page 2 Rev. 3.00 Mar. 14, 2006 Page ii of xxxviii Downloaded from Elcodis.com electronic components distributor...
Page 3 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 4 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 5 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 6 Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ Rev. 3.00 Mar. 14, 2006 Page vi of xxxviii Downloaded from Elcodis.com...
Page 7 H8SX/1520 Group manuals: Document Title Document No. H8SX/1520 Group Hardware Manual This manual H8/SX Family Software Manual REJ09B0102 Rev. 3.00 Mar. 14, 2006 Page vii of xxxviii Downloaded from Elcodis.com electronic components distributor...
Page 8 Rev. 3.00 Mar. 14, 2006 Page viii of xxxviii Downloaded from Elcodis.com electronic components distributor...
Page 9: Table Of Contents
Contents Section 1 Overview....................1 Features..........................1 Block Diagram ........................2 Pin Assignments........................4 1.3.1 Pin Assignments ....................... 4 1.3.2 Pin Configuration in Each Operating Mode.............. 6 1.3.3 Pin Functions ......................10 Section 2 CPU......................19 Features..........................19 CPU Operating Modes......................21 2.2.1 Normal Mode......................
Page 10 2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn) ..................... 55 2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..... 56 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− ........ 56 2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32........
Page 11 Interrupts..........................81 4.6.1 Interrupt Sources..................... 81 4.6.2 Interrupt Exception Handling ................. 82 Instruction Exception Handling ................... 83 4.7.1 Trap Instruction....................... 83 4.7.2 Exception Handling by Illegal Instruction .............. 84 Stack Status after Exception Handling................. 85 Usage Note........................... 86 Section 5 Interrupt Controller ................87 Features..........................
Page 12 Section 6 Bus Controller (BSC) ................ 125 Features..........................125 Register Descriptions......................126 6.2.1 Bus Control Register 2 (BCR2) ................126 Bus Configuration......................127 Multi-Clock Function ......................128 Internal Bus........................129 6.5.1 Access to Internal Address Space ................. 129 Write Data Buffer Function ....................130 6.6.1 Write Data Buffer Function for Peripheral Module ..........
Page 13 7.4.11 Bus Cycles in Single Address Mode..............191 DMA Transfer End ......................196 Relationship among DMAC and Other Bus Masters ............198 7.6.1 CPU Priority Control Function Over DMAC ............198 7.6.2 Bus Arbitration among DMAC and Other Bus Masters ........199 Interrupt Sources........................
Page 14 9.3.2 Timer Mode Register (TMDR)................270 9.3.3 Timer I/O Control Register (TIOR)..............272 9.3.4 Timer Interrupt Enable Register (TIER)............... 290 9.3.5 Timer Status Register (TSR)................. 292 9.3.6 Timer Counter (TCNT)..................296 9.3.7 Timer General Register (TGR) ................296 9.3.8 Timer Start Register (TSTR) ................297 9.3.9 Timer Synchronous Register (TSYR)..............
Page 15 10.3 Register Descriptions ......................347 10.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ......... 347 10.3.2 Output Data Registers H, L (PODRH, PODRL)........... 349 10.3.3 Next Data Registers H, L (NDRH, NDRL) ............350 10.3.4 PPG Output Control Register (PCR) ..............353 10.3.5 PPG Output Mode Register (PMR) ..............
Page 16 12.3 Register Descriptions......................380 12.3.1 Receive Shift Register (RSR) ................381 12.3.2 Receive Data Register (RDR)................381 12.3.3 Transmit Data Register (TDR)................381 12.3.4 Transmit Shift Register (TSR) ................382 12.3.5 Serial Mode Register (SMR) ................382 12.3.6 Serial Control Register (SCR) ................385 12.3.7 Serial Status Register (SSR) .................
Page 17 12.9 Usage Notes ........................442 12.9.1 Module Stop Mode Setting ................... 442 12.9.2 Break Detection and Processing ................442 12.9.3 Mark State and Break Detection ................442 12.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..............442 12.9.5 Relation between Writing to TDR and TDRE Flag ..........
Page 18 13.4.6 HCAN Halt Mode....................500 13.5 Interrupt Sources........................ 501 13.6 DMAC Interface ........................ 502 13.7 CAN Bus Interface......................503 13.8 Usage Notes ........................504 13.8.1 Module Stop Mode Setting ................... 504 13.8.2 Reset ........................504 13.8.3 HCAN Sleep Mode....................504 13.8.4 Interrupts.......................
Page 19 14.6 Usage Note......................... 546 14.6.1 Setting of Module Stop Mode................546 14.6.2 Notes on Clearing Module Stop Mode ..............546 Section 15 A/D Converter..................547 15.1 Features..........................547 15.2 Input/Output Pins ....................... 550 15.3 Register Descriptions ......................551 15.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ..........552 15.3.2 A/D Control/Status Register (ADCSR) ..............
Page 20 17.8 On-Board Programming Mode ..................599 17.8.1 Boot Mode ......................599 17.8.2 User Program Mode....................603 17.8.3 User Boot Mode....................613 17.8.4 On-Chip Program and Storable Area for Program Data ........617 17.9 Protection........................... 623 17.9.1 Hardware Protection ..................... 623 17.9.2 Software Protection ....................
Page 21 19.6 All-Module-Clock-Stop Mode ................... 680 19.7 Software Standby Mode..................... 681 19.7.1 Transition to Software Standby Mode ..............681 19.7.2 Clearing Software Standby Mode ................. 681 19.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode ... 682 19.7.4 Software Standby Mode Application Example............. 684 19.8 Bφ...
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Page 23 Figures Section 1 Overview Figure 1.1 Block Diagram of H8SX/1527 ..................2 Figure 1.2 Block Diagram of H8SX/1525 ..................3 Figure 1.3 Pin Assignments of H8SX/1527..................4 Figure 1.4 Pin Assignments of H8SX/1525..................5 Section 2 CPU Figure 2.1 CPU Operating Modes ....................21 Figure 2.2 Exception Vector Table (Normal Mode)..............
Page 24 Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of Bus Controller................125 Figure 6.2 Internal Bus Configuration..................127 Figure 6.3 Example of Timing when Write Data Buffer Function is Used ........ 130 Section 7 DMA Controller (DMAC) Figure 7.1 Block Diagram of DMAC ..................135 Figure 7.2 Example of Signal Timing in Dual Address Mode ...........
Page 25 Figure 7.31 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level ....................189 Figure 7.32 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level with NRD = 1............... 190 Figure 7.33 Example of Transfer in Single Address Mode (Byte Read) ........191 Figure 7.34 Example of Transfer in Single Address Mode (Byte Write) ........
Page 26 Figure 9.26 Example of Phase Counting Mode 1 Operation ............320 Figure 9.27 Example of Phase Counting Mode 2 Operation ............321 Figure 9.28 Example of Phase Counting Mode 3 Operation ............322 Figure 9.29 Example of Phase Counting Mode 4 Operation ............323 Figure 9.30 Phase Counting Mode Application Example............
Page 27 Section 11 Watchdog Timer (WDT) Figure 11.1 Block Diagram of WDT ..................367 Figure 11.2 Operation in Watchdog Timer Mode............... 372 Figure 11.3 Operation in Interval Timer Mode................373 Figure 11.4 Writing to TCNT, TCSR, and RSTCSR..............374 Figure 11.5 Conflict between TCNT Write and Increment ............375 Section 12 Serial Communication Interface (SCI) Figure 12.1 Block Diagram of SCI.....................
Page 28 Figure 12.27 TEND Flag Set Timing during Transmission............435 Figure 12.28 Sample Transmission Flowchart ................436 Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode..........437 Figure 12.30 Sample Reception Flowchart................. 438 Figure 12.31 Clock Output Fixing Timing ................. 438 Figure 12.32 Clock Stop and Restart Procedure.................
Page 29 Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode ... 539 Figure 14.13 Example of Transmission Operation (Clock Synchronous Communication Mode)............540 Figure 14.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode)............541 Figure 14.15 Example of Reception Operation (Clock Synchronous Communication Mode)............
Page 30 Figure 17.17 RAM Emulation Flow ................... 626 Figure 17.18 Address Map of Overlaid RAM Area ..............627 Figure 17.19 Programming Tuned Data ..................628 Figure 17.20 Switching between User MAT and User Boot MAT ..........629 Figure 17.21 Boot Program States....................631 Figure 17.22 Bit-Rate-Adjustment Sequence ................
Page 31 Figure 21.20 SSU Timing (Slave, CPHS = 0) ................775 Appendix Figure C.1 Package Dimensions (PRQP0100KB-A)..............781 Rev. 3.00 Mar. 14, 2006 Page xxxi of xxxviii Downloaded from Elcodis.com electronic components distributor...
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Page 33 Tables Section 1 Overview Table 1.1 Pin Configuration in Each Operating Mode.............. 6 Table 1.2 Pin Functions ......................10 Section 2 CPU Table 2.1 Instruction Classification ..................36 Table 2.2 Combinations of Instructions and Addressing Modes (1)........38 Table 2.2 Combinations of Instructions and Addressing Modes (2)........
Page 34 Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority......105 Table 5.3 Interrupt Control Modes ..................112 Table 5.4 Interrupt Response Times ..................117 Table 5.5 Number of Execution States in Interrupt Handling Routine ......... 118 Table 5.6 Interrupt Source Selection and Clear Control ............119 Table 5.7 CPU Priority Control ....................
Page 35 Table 9.15 TIORH_0 ......................274 Table 9.16 TIORL_0....................... 275 Table 9.17 TIOR_1 ......................... 276 Table 9.18 TIOR_2 ......................... 277 Table 9.19 TIORH_3 ......................278 Table 9.20 TIORL_3....................... 279 Table 9.21 TIOR_4 ......................... 280 Table 9.22 TIOR_5 ......................... 281 Table 9.23 TIORH_0 ......................
Page 36 Table 12.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) ............404 Table 12.9 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372)..............404 Table 12.10 Serial Transfer Formats (Asynchronous Mode)..........406 Table 12.11 SSR Status Flags and Receive Data Handling ..........
Page 37 Table 17.8 Usable Area for Programming in User Program Mode......... 619 Table 17.9 Usable Area for Erasure in User Program Mode ..........620 Table 17.10 Usable Area for Programming in User Boot Mode........... 621 Table 17.11 Usable Area for Erasure in User Boot Mode ............ 622 Table 17.12 Hardware Protection ..................
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Page 39: Section 1 Overview
Section 1 Overview Section 1 Overview Features • 32-bit high-speed H8SX CPU Upward compatible with the H8/300 CPU, H8/300H CPU, and H8S CPU Sixteen 16-bit general registers 87 basic instructions • Extensive peripheral functions DMA controller (DMAC) 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG)* Watch dog timer (WDT) Serial communication interface (SCI) can be used in asynchronous and clocked synchronous...
Page 40: Block Diagram
Section 1 Overview Block Diagram Port 1 TPU (unit 0) Port 2 × 6 channels Interrupt controller TPU (unit 1) Port 3 × 6 channels Port 4 Port 5 SCI × 2 channels H8SX Port 6 HCAN Port A SSU × 3 channels DMAC ×...
Page 41: Figure 1.2 Block Diagram Of H8Sx/1525
Section 1 Overview Port 1 Port 2 TPU (unit 1) Interrupt x 6 channels controller Port 3 SCI x 2 channels Port 4 Port 5 HCAN H8SX Port 6 SSU x 3 channels Port A DMAC x 4 channels Port D A/D (unit 0) x 8 channels Clock pulse A/D (unit 1) x 8 channels...
Page 42: Pin Assignments
Section 1 Overview Pin Assignments 1.3.1 Pin Assignments 75747372717069686766656463626160595857565554535251 P22/TIOCC3/IRQ10-A P40/AN12 P21/TIOCA3/IRQ9-A/SCS2 P41/AN13 P20/TIOCA3/TIOCB3/IRQ8-A P42/AN14 P17/ADTRG1/IRQ7 P43/AN15 P16/SCK3/IRQ6 P44/AN8 P15/RxD3/IRQ5 P45/AN9 P14/TxD3/IRQ4 P46/AN10 P13/ADTRG0/IRQ3 AVcc1 P12/IRQ2 P47/AN11 AVss P11/IRQ1 P50/AN0 PRQP0100KB-A (FP-100M) AVcc0 P10/IRQ0 (top view) P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7...
Page 43: Figure 1.4 Pin Assignments Of H8Sx/1525
Section 1 Overview 75747372717069686766656463626160595857565554535251 P22/IRQ10-A P40/AN12 P21/IRQ9-A/SCS2 P41/AN13 P20/IRQ8-A P42/AN14 P17/ADTRG1/IRQ7 P43/AN15 P16/SCK3/IRQ6 P44/AN8 P15/RxD3/IRQ5 P45/AN9 P14/TxD3/IRQ4 P46/AN10 P13/ADTRG0/IRQ3 AVcc1 P12/IRQ2 P47/AN11 AVss P11/IRQ1 P50/AN0 PRQP0100KB-A (FP-100M) AVcc0 P10/IRQ0 (top view) P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 PD0/SSO0 PK7/TIOCA11/TIOCB11 PD1/SSI0 PK6/TIOCA11 PD2/SSCK0...
Page 44: Pin Configuration In Each Operating Mode
Section 1 Overview 1.3.2 Pin Configuration in Each Operating Mode Table 1.1 Pin Configuration in Each Operating Mode Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3 PD4/SSO1 PD5/SSI1 PD6/SSCK1 PD7/SCS1 P60/TxD4/IRQ8-B P61/RxD4/IRQ9-B P62/SCK4/IRQ10-B P63/IRQ11-B/TDO* P64/IRQ12/HTxD P65/IRQ13/HRxD P66/IRQ14 PJ0/TIOCA6 PJ1/TIOCA6/TIOCB6 PJ2/TIOCC6/TCLKE...
Page 45 Section 1 Overview Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3 P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/ADTRG0/IRQ3 P14/TxD3/IRQ4 P15/RxD3/IRQ5 P16/SCK3/IRQ6 P17/ADTRG1/IRQ7 P20/(TIOCA3/TIOCB3)* /IRQ8-A P21/(TIOCA3)* /IRQ9-A/SCS2 P22/(TIOCC3)* /IRQ10-A P23/(TIOCC3/TIOCD3)* /IRQ11-A PA7/Bφ P30/(PO8/TIOCA0)* P31/(PO9/TIOCA0/TIOCB0)* P32/(PO10/TIOCC0/TCLKA)* Rev. 3.00 Mar. 14, 2006 Page 7 of 804 REJ09B0104-0300 Downloaded from Elcodis.com...
Page 46 Section 1 Overview Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3 P33/(PO11/TIOCC0/TIOCD0/TCLKB)* P34/(PO12/TIOCA1)* /TRST* P35/(PO13/TIOCA1/TIOCB1/TCLKC)* /TMS* P36/(PO14/TIOCA2)* /TDI* P37/(PO15/TIOCA2/TIOCB2/TCLKD)* /TCK* XTAL EXTAL EMLE* PA3/SSO2 PA2/SSI2 PA1/SSCK2 P40/AN12 P41/AN13 P42/AN14 P43/AN15 P44/AN8 P45/AN9 P46/AN10 AVcc1 P47/AN11 AVss P50/AN0 AVcc0 P51/AN1 P52/AN2...
Page 47 Section 1 Overview Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 PD0/SSO0 PD1/SSI0 PD2/SSCK0 PD3/SCS0 Notes: 1. Not supported by the H8SX/1525. 2. The EMLE (emulator enable) pin enables/disables the on-chip debugging functions. When the EMLE pin is driven high, the TDO, TDI, TCK, TMS, and TRST pins are used specific for the E10A.
Page 48: Pin Functions
Section 1 Overview 1.3.3 Pin Functions Table 1.2 Pin Functions Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 Description Power 22, 54, 68 22, 54, 68 Input Power supply pins. Connect to the system supply power supply. Input Connect to VSS via a 0.1-uF capacitor (place it close to this pin).
Page 49 Section 1 Overview Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 Description Interrupts Input Non-maskable interrupt request signal. When this pin is not in use, this signal must be fixed high. IRQ14 Input Maskable interrupt request signal. IRQ13 IRQ12 IRQ11-A/IRQ11-B 51/8 51/8 IRQ10-A/IRQ10-B 50/7...
Page 50 Section 1 Overview Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 Description  16-bit TIOCA2 64, 65 Signals for TGRA_2 and TGRB_2. These timer are used for the input capture  TIOCB2 pulse unit inputs/output compare outputs/PWM (TPU) outputs. (unit 0)* ...
Page 51 Section 1 Overview Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 Description  Program- PO15 Output Output pins for the pulse signals. mable  PO14 pulse  PO13 generator  (PPG)* PO12  PO11  PO10   Serial TxD3 Output Output pins for transmit data. communi- TxD4 cation...
Page 52 Section 1 Overview Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 Description AN15 Input Input pins for the analog signals for the converter A/D converter. AN14 AN13 AN12 AN11 AN10 ADTRG0 Input Input pins for the external trigger signal to start A/D conversion. ADTRG1 Input Analog power supply and reference power...
Page 53 Section 1 Overview Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 Description I/O port 8-bit input/output pins. 4-bit input/output pins. 8-bit input/output pins. Input 8-bit input pins. Rev. 3.00 Mar. 14, 2006 Page 15 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 54 Section 1 Overview Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 Description I/O port Input 8-bit input pins. 7-bit input/output pins. Input 1-bit input pin. 6-bit input/output pins. 8-bit input/output pins. Rev. 3.00 Mar. 14, 2006 Page 16 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 55 Section 1 Overview Pin Number Classifi- cation Abbreviation H8SX/1527 H8SX/1525 Description I/O port 8-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. Note: Supported only by the H8SX/1527. Rev. 3.00 Mar. 14, 2006 Page 17 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 56 Section 1 Overview Rev. 3.00 Mar. 14, 2006 Page 18 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 57: Section 2 Cpu
Section 2 CPU Section 2 CPU The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward- compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ideal for a realtime control system.
Page 58: Section 2 Cpu
Section 2 CPU • Two base registers  Vector base register  Short address base register • 4-Gbyte address space  Program: 4 Gbytes  Data: 4 Gbytes • High-speed operation  All frequently-used instructions executed in one or two states ...
Page 59: Cpu Operating Modes
Section 2 CPU CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. For details on mode settings, see section 3.1, Operating Mode Selection. Maximum 64 kbytes for program Normal mode and data areas combined Maximum 16-Mbyte program area and 64-kbyte data area, Middle mode...
Page 60: Figure 2.2 Exception Vector Table (Normal Mode)
Section 2 CPU • Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the exception vector table is shown in figure 2.2.
Page 61: Middle Mode
Section 2 CPU 2.2.2 Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. • Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program and data areas.
Page 62: Advanced Mode
Section 2 CPU 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. • Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to 16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated.
Page 63: Maximum Mode
Section 2 CPU • Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. EXR* Reserved Reserved*...
Page 64: Figure 2.6 Exception Vector Table (Maximum Modes)
Section 2 CPU H'00000000 H'00000001 Reset exception vector H'00000002 H'00000003 H'00000004 Exception vector table H'00000005 H'00000006 H'00000007 Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location.
Page 65: Instruction Fetch
Section 2 CPU Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch mode setting does not affect operation other than instruction fetch such as data accesses.
Page 66: Registers
Section 2 CPU Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register (MAC).
Page 67: General Registers
Section 2 CPU 2.5.1 General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
Page 68: Program Counter (Pc)
Section 2 CPU Free area SP (ER7) Stack area Figure 2.11 Stack 2.5.2 Program Counter (PC) PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant bit is ignored.
Page 69 Section 2 CPU Initial Bit Name Value Description Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise.
Page 70: Extended Control Register (Exr)
Section 2 CPU 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0). Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 71: Multiply-Accumulate Register (Mac)
Section 2 CPU 2.5.7 Multiply-Accumulate Register (MAC) MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC, and STMAC instructions.
Page 72: Figure 2.12 General Register Data Formats
Section 2 CPU 1-bit data 7 6 5 4 3 2 1 0 Don’t care 1-bit data Don’t care 7 6 5 4 3 2 1 0 4-bit BCD data Upper Lower Don’t care 4-bit BCD data Don’t care Upper Lower Byte data Don’t care...
Page 73: Memory Data Formats
Section 2 CPU 2.6.2 Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword data begins at an address other than a multiple of 4, a bus cycle is divided into two or more accesses.
Page 74: Instruction Set
Section 2 CPU Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in this manual. Table 2.1 Instruction Classification Function...
Page 75 Section 2 CPU Function Instructions Size Types Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC  Bcc* , JMP, BSR, JSR, RTS RTS/L  BRA/S  System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC B/W/L Total [Legend] Byte size Word size Longword size Notes: 1.
Page 76: Instructions And Addressing Modes
Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Addressing Mode @(d, @−ERn/ RnL.B/ @ERn+/ Classifi- Rn.W/ @ERn−/ @aa:16/...
Page 77 Section 2 CPU Addressing Mode @(d, @−ERn/ RnL.B/ @ERn+/ Classifi- Rn.W/ @ERn−/ @aa:16/  cation Instruction Size @ERn @(d,ERn) ERn.L) @+ERn @aa:8 @aa:32 Arithmetic MULXU, DIVXU operations MULU, DIVU MULXS, DIVXS MULS, DIVS EXTU, EXTS   CLRMAC  LDMAC ...
Page 78 Section 2 CPU Addressing Mode @(d, @−ERn/ RnL.B/ @ERn+/ Classifi- Rn.W/ @ERn−/ @aa:16/  cation Instruction Size @ERn @(d,ERn) ERn.L) @+ERn @aa:8 @aa:32 BFLD manipu- BFST lation Branch BRA/BS, BRA/BC* BSR/BS, BSR/BC* System LDC (CCR, EXR) B/W* control LDC (VBR, SBR) STC (CCR, EXR) B/W* STC (VBR, SBR)
Page 79: Table 2.2 Combinations Of Instructions And Addressing Modes (2)
Section 2 CPU Table 2.2 Combinations of Instructions and Addressing Modes (2) Addressing Mode @(RnL. B/Rn.W/ Classifi- ERn.L,  cation Instruction Size @ERn @(d,PC) @aa:24 @ aa:32 @@ aa:8 @@vec:7  Branch BRA/BS, BRA/BC  BSR/BS, BSR/BC    BRA/S ...
Page 80: Table Of Instructions Classified By Function
Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register)
Page 81: Table 2.4 Data Transfer Instructions
Section 2 CPU Table 2.4 Data Transfer Instructions Instruction Size Function #IMM → (EAd), (EAs) → (EAd) B/W/L Transfers data between immediate data, general registers, and memory. (EAs) → Rd MOVFPE* Rs → (EAs) MOVTPE* @SP+ → Rn Restores the data from the stack to a general register. Rn →...
Page 82: Table 2.5 Block Transfer Instructions
Section 2 CPU Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B Transfers a data block. EEPMOV.W Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4 or R4L.
Page 83: Table 2.6 Arithmetic Operation Instructions
Section 2 CPU Table 2.6 Arithmetic Operation Instructions Instruction Size Function (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) B/W/L Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted from byte data in a general register.
Page 84 Section 2 CPU Instruction Size Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 85: Table 2.7 Logic Operation Instructions
Section 2 CPU Instruction Size Function  Rs → MAC LDMAC Loads data from a general register to MAC.  MAC → Rd STMAC Stores data from MAC to a general register. Table 2.7 Logic Operation Instructions Instruction Size Function (EAd) ∧...
Page 86: Table 2.8 Shift Operation Instructions
Section 2 CPU Table 2.8 Shift Operation Instructions Instruction Size Function (EAd) (shift) → (EAd) SHLL B/W/L SHLR Performs a logical shift on the contents of a general register or a memory location. The contents of a general register or a memory location can be shifted by 1, 2, 4, 8, or 16 bits.
Page 87: Table 2.9 Bit Manipulation Instructions
Section 2 CPU Table 2.9 Bit Manipulation Instructions Instruction Size Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 88 Section 2 CPU Instruction Size Function C ∨ [~ (<bit-No.> of <EAd>)] → C BIOR ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag.
Page 89: Table 2.10 Branch Instructions
Section 2 CPU Instruction Size Function ∼ Z → (<bit-No.> of <EAd>) BISTZ Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data. (EAs) (bit field) →...
Page 90: Table 2.11 System Control Instructions
Section 2 CPU Table 2.11 System Control Instructions Instruction Size Function  TRAPA Starts trap-instruction exception handling.  Returns from an exception-handling routine.  RTE/L Returns from an exception-handling routine, restoring data from the stack to multiple general registers.  SLEEP Causes a transition to a power-down state.
Page 91: Basic Instruction Formats
Section 2 CPU 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.14 shows examples of instruction formats.
Page 92: Addressing Modes And Effective Address Calculation
Section 2 CPU Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Page 93: Register Direct-Rn
Section 2 CPU 2.8.1 Register Direct—Rn The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers.
Page 94: Index Register Indirect With Displacement-@(D:16,Rnl.b), @(D:32,Rnl.b), @(D:16,Rn.w), @(D:32,Rn.w), @(D:16,Ern.l), Or @(D:32,Ern.l)
Section 2 CPU 2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L) The operand value is the contents of a memory location which is pointed to by the sum of the following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an address register (RnL, Rn, ERn) specified by the register field in the instruction code are zero- extended to 32-bit data and multiplied by 1, 2, or 4.
Page 95 Section 2 CPU Register indirect with post-decrement—@ERn− The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the remainder is stored in the address register.
Page 96: Absolute Address-@Aa:8, @Aa:16, @Aa:24, Or @Aa:32
Section 2 CPU 2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 The operand value is the contents of a memory location which is pointed to by an absolute address included in the instruction code. There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and 32-bit (@aa:32) absolute addresses.
Page 97: Immediate-#Xx
Section 2 CPU 2.8.7 Immediate—#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate data is less than that of the destination operand value (byte, word, or longword) the immediate data is zero-extended.
Page 98: Memory Indirect-@@Aa:8
Section 2 CPU 2.8.10 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by an 8-bit absolute address in the instruction code.
Page 99: Extended Memory Indirect-@@Vec:7
Section 2 CPU 2.8.11 Extended Memory Indirect—@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of 7-bit data in the instruction code and the value of H'80 is multiplied by 2 or 4.
Page 100: Table 2.14 Effective Address Calculation For Transfer And Operation Instructions
Section 2 CPU Table 2.14 Effective Address Calculation for Transfer and Operation Instructions Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Immediate Register direct Register indirect General register contents Register indirect with 16-bit displacement General register contents disp Sign extension disp...
Page 101: Mova Instruction
Section 2 CPU Table 2.15 Effective Address Calculation for Branch Instructions Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register indirect General register contents Program-counter relative with 8-bit displacement PC contents disp Sign extension disp Program-counter relative with 16-bit displacement PC contents Sign extension disp...
Page 102: Processing States
Section 2 CPU Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. • Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state.
Page 103: Figure 2.16 State Transitions
Section 2 CPU Reset state* RES = high RES = low Exception-handling Bus-released state Interrupt state request request Request for exception End of exception handling handling Bus request End of bus request End of bus request Program execution Program stop state state SLEEP instruction A transition to the reset state occurs whenever the RES signal goes low.
Page 104 Section 2 CPU Rev. 3.00 Mar. 14, 2006 Page 66 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 105: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Section 3 MCU Operating Modes Operating Mode Selection This LSI has three operating modes (modes 1 to 3). The operating mode is selected by the setting of mode pins (MD1 and MD0). Table 3.1 lists MCU operating mode settings. In this LSI, advanced mode for the CPU operating mode and 16-Mbyte address space are available.
Page 106: Register Descriptions
Section 3 MCU Operating Modes Register Descriptions The following registers are related to the operating mode setting. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR indicates the current operating mode. When MDCR is read, the states of signals input on pins MD1 and MD0 are latched.
Page 107: System Control Register (Syscr)
Section 3 MCU Operating Modes Bit Name Initial Value R/W Descriptions  Reserved  These are read-only bits and cannot be modified.    Undefined*  Undefined*  Undefined*  Undefined* Note: Determined by pins MD1 and MD0. Table 3.2 Settings of Bits MSD3 to MSD0 MDCR MCU Operating Mode MD1...
Page 108 Section 3 MCU Operating Modes Initial Bit Name Value Descriptions  15, 14 All 1 Reserved These are read-only bits and cannot be modified. MACS MAC Saturation Operation Control Selects either saturation operation or non-saturation operation for the MAC instruction. 0: MAC instruction is non-saturation operation 1: MAC instruction is saturation operation ...
Page 109: Operating Mode Descriptions
Section 3 MCU Operating Modes Operating Mode Descriptions 3.3.1 Mode 1 Mode 1 is the user boot mode for the flash memory. The operations are the same as that in mode 3 other than programming/erasing the flash memory. 3.3.2 Mode 2 Mode 2 is the boot mode for the flash memory.
Page 110: Address Map
Section 3 MCU Operating Modes Address Map 3.4.1 Address Map (Advanced Mode) Figure 3.1 shows the address map. Mode 1 to mode 3 Single chip initiation mode (advanced mode) H'000000 On-chip ROM (256 kbytes) H'040000 Reserved H'FF9000 On-chip RAM (12 kbytes) H'FFC000 Reserved H'FFEA00...
Page 111: Section 4 Exception Handling
Section 4 Exception Handling Section 4 Exception Handling Exception Handling Types and Priority As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, and illegal instructions (general illegal instruction and slot illegal instruction).
Page 112: Exception Sources And Exception Handling Vector Table
Section 4 Exception Handling Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector table address offset of the vector number.
Page 113 Section 4 Exception Handling Vector Table Address Offset* Advanced, Middle, Exception Source Vector Number Normal Mode* Maximum Modes External interrupt IRQ0 H'0080 to H'0081 H'0100 to H'0103 IRQ1 H'0082 to H'0083 H'0104 to H'0107 IRQ2 H'0084 to H'0085 H'0108 to H'010B IRQ3 H'0086 to H'0087 H'010C to H'010F...
Page 114: Reset
Section 4 Exception Handling Table 4.3 Calculation Method of Exception Handling Vector Table Address Exception Source Calculation Method of Vector Table Address Reset, CPU address error Vector table address = (vector table address offset) Vector table address = VBR + (vector table address offset) Other than above [Legend] VBR: Vector base register...
Page 115: Interrupts After Reset
Section 4 Exception Handling 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Page 116: Traces
Section 4 Exception Handling Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared to 0. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated.
Page 117: Address Error
Section 4 Exception Handling Address Error 4.5.1 Address Error Source Instruction fetch, stack operation, data read/write, and single-address transfer shown in table 4.5 may cause an address error. Table 4.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Description Address Error Instruction fetch CPU...
Page 118: Address Error Exception Handling
Section 4 Exception Handling Bus Cycle Type Bus Master Description Address Error Single address DMAC In single address transfer, the device to be No (normal) transfer accessed with an address is in the external memory space In single address transfer, the device to be Occurs accessed with an address is not in the external memory space...
Page 119: Interrupts
Section 4 Exception Handling Table 4.6 shows the states of CCR and EXR after the address error exception handling. Table 4.6 States of CCR and EXR after Address Error Exception Handling Interrupt Control Mode I I2 to I0   ...
Page 120: Interrupt Exception Handling
Section 4 Exception Handling 4.6.2 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiple-interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product.
Page 121: Instruction Exception Handling
Section 4 Exception Handling Instruction Exception Handling There are two types of instructions that cause exception handling: trap instruction and illegal instructions. 4.7.1 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1.
Page 122: Exception Handling By Illegal Instruction
Section 4 Exception Handling 4.7.2 Exception Handling by Illegal Instruction There are two illegal instructions: general illegal instruction and slot illegal instruction. The exception handling by the general illegal instruction starts when an undefined code is decoded. The exception handling by the slot illegal instruction starts when the following instruction which is placed in a delay slot (immediately after a delayed branch instruction) is executed: an instruction which consists of two words or more or which changes the contents of PC.
Page 123: Stack Status After Exception Handling
Section 4 Exception Handling Stack Status after Exception Handling Figure 4.2 shows the stack after completion of exception handling. Advanced mode Reserved* PC (24 bits) PC (24 bits) Interrupt control mode 0 Interrupt control mode 2 Note: * Ignored on return. Figure 4.2 Stack Status after Exception Handling Rev.
Page 124: Usage Note
Section 4 Exception Handling Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: •...
Page 125: Section 5 Interrupt Controller
Section 5 Interrupt Controller Section 5 Interrupt Controller Features • Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). • Priority can be assigned by the interrupt priority register (IPR) IPR provides for setting interrupt priory.
Page 126: Input/Output Pins
Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 INTCR NMIEG I2 to I0 interrupt request NMI input NMI input unit vector IRQ input IRQ input unit Priority DMAC decision unit DMAC ISCR SSIER...
Page 127: Register Descriptions
Section 5 Interrupt Controller Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) • CPU priority control register (CPUPCR) • Interrupt priority registers A to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR) •...
Page 128: Cpu Priority Control Register (Cpupcr)
Section 5 Interrupt Controller Initial Bit Name Value Description NMIEG NMI Edge Select Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input ...
Page 129 Section 5 Interrupt Controller Initial Bit Name Value Description IPSETE Interrupt Priority Set Enable Controls the function which automatically assigns the interrupt priority level of the CPU. Setting this bit to 1 automatically sets bits CPUP2 to CPUP0 by the CPU interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR).
Page 130: Interrupt Priority Registers A To G, I, K To O, Q, And R (Ipra To Iprg, Ipri, Iprk To Ipro, Iprq, And Iprr)
Section 5 Interrupt Controller 5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR) IPR sets priory (levels 7 to 0) for interrupts other than NMI. Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 assigns a priority level to the corresponding interrupt.
Page 131 Section 5 Interrupt Controller Initial Bit Name Value Description IPR10 Sets the priority level of the corresponding interrupt source. IPR9 000: Priority level 0 (lowest) IPR8 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)
Page 132: Irq Enable Register (Ier)
Section 5 Interrupt Controller 5.3.4 IRQ Enable Register (IER) IER enables or disables interrupt requests IRQ14 to IRQ0. Bit Name — IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8E Initial Value Bit Name IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial Value Initial Bit Name...
Page 133 Section 5 Interrupt Controller Initial Bit Name Value Description IRQ8E IRQ8 Enable The IRQ8 interrupt request is enabled when this bit is 1. IRQ7E IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1. IRQ6E IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is 1.
Page 134: Irq Sense Control Registers H And L (Iscrh And Iscrl)
Section 5 Interrupt Controller 5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL) ISCRH and ISCRL select the source that generates an interrupt request on pins IRQ14 to IRQ0. Upon changing the setting of ISCR, IRQnF (n = 14 to 0) in ISR is often set to 1 accidentally through an internal operation.
Page 135 Section 5 Interrupt Controller • ISCRH Initial Bit Name Value Description  15, 14 All 0 Reserved These bits are always read as 0. The write value should always be 0. IRQ14SR IRQ14 Sense Control Rise IRQ14 Sense Control Fall IRQ14SF 00: Interrupt request generated by low level of IRQ14 01: Interrupt request generated at falling edge of IRQ14...
Page 136 Section 5 Interrupt Controller Initial Bit Name Value Description IRQ10SR IRQ10 Sense Control Rise IRQ10 Sense Control Fall IRQ10SF 00: Interrupt request generated by low level of IRQ10 01: Interrupt request generated at falling edge of IRQ10 10: Interrupt request generated at rising edge of IRQ10 11: Interrupt request generated at both falling and rising edges of IRQ10 IRQ9SR...
Page 137 Section 5 Interrupt Controller • ISCRL Initial Bit Name Value Description IRQ7SR IRQ7 Sense Control Rise IRQ7 Sense Control Fall IRQ7SF 00: Interrupt request generated by low level of IRQ7 01: Interrupt request generated at falling edge of IRQ7 10: Interrupt request generated at rising edge of IRQ7 11: Interrupt request generated at both falling and rising edges of IRQ7 IRQ6SR...
Page 138 Section 5 Interrupt Controller Initial Bit Name Value Description IRQ3SR IRQ3 Sense Control Rise IRQ3 Sense Control Fall IRQ3SF 00: Interrupt request generated by low level of IRQ3 01: Interrupt request generated at falling edge of IRQ3 10: Interrupt request generated at rising edge of IRQ3 11: Interrupt request generated at both falling and rising edges of IRQ3 IRQ2SR...
Page 139: Irq Status Register (Isr)
Section 5 Interrupt Controller 5.3.6 IRQ Status Register (ISR) ISR is an IRQ14 to IRQ0 interrupt request register. Bit Name — IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F Initial Value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Bit Name IRQ7F IRQ6F IRQ5F...
Page 140: Software Standby Release Irq Enable Register (Ssier)
Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects pins used to leave software standby mode from pins IRQ14 to IRQ0. Bit Name — SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 Initial Value Bit Name SSI7 SSI6 SSI5...
Page 141: Interrupt Sources
Section 5 Interrupt Controller Interrupt Sources 5.4.1 External Interrupts There are sixteen external interrupts: NMI and IRQ14 to IRQ0. These interrupts can be used to leave software standby mode. NMI Interrupts: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits.
Page 142: Internal Interrupts
Section 5 Interrupt Controller IRQnE Corresponding bit IRQnSF, IRQnSR in ICR IRQnF IRQn interrupt request Edge/level Input buffer detection circuit IRQn input Clear signal [Legend] n = 14 to 0 Figure 5.2 Block Diagram of Interrupts IRQn When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn should be held low until an interrupt handling starts.
Page 143: Interrupt Exception Handling Vector Table
Section 5 Interrupt Controller Interrupt Exception Handling Vector Table Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The priority for interrupt sources allocated to the same level in IPR follows the default priority, that is, they are fixed.
Page 144 Section 5 Interrupt Controller Vector Vector Address DMAC Classification Interrupt Source Number Offset* Priority Activation A/D_0 ADI0 H'0158 IPRF10 to IPRF8 High A/D_1 ADI1 H'015C TPU_0* TGI0A H'0160 IPRF6 to IPRF4  TGI0B H'0164  TGI0C H'0168  TGI0D H'016C ...
Page 145 Section 5 Interrupt Controller Vector Vector Address DMAC Classification Interrupt Source Number Offset* Priority Activation   Reserved for system use H'01DC High  H'01E0  H'01E4  H'01E8  H'01EC  H'01F0  H'01F4  H'01F8  H'01FC  DMAC DMTEND0 H'0200...
Page 146 Section 5 Interrupt Controller Vector Vector Address DMAC Classification Interrupt Source Number Offset* Priority Activation    Reserved for system use H'0260 High  H'0264  H'0268  H'026C  SCI_3 ERI3 H'0270 IPRL10 to IPRL8 RXI3 H'0274 TXI3 H'0278 ...
Page 147 Section 5 Interrupt Controller Vector Vector Address DMAC Classification Interrupt Source Number Offset* Priority Activation TPU_10 TGI10A H'02D8 IPRN2 to IPRN0 High  TGI10B H'02DC  Reserved for system use H'02E0  Reserved for system use H'02E4  TCI10V H'02E8 IPRO14 to IPRO12 ...
Page 148 Section 5 Interrupt Controller Vector Vector Address DMAC Classification Interrupt Source Number Offset* Priority Activation    Reserved for system use H'0358 High  H'035C  H'0360  H'0364  H'0368  H'036C  HCAN ERS0/OVR0 H'0370 IPRQ2 to IPRQ0 H'0374 ...
Page 149 Section 5 Interrupt Controller Vector Vector Address DMAC Classification Interrupt Source Number Offset* Priority Activation    Reserved for system use H'03D8 High  H'03DC  H'03E0  H'03E4  H'03E8  H'03EC  H'03F0  H'03F4  H'03F8 ...
Page 150: Interrupt Control Modes And Interrupt Operation
Section 5 Interrupt Controller Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2.
Page 151 Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? I = 0 Pending...
Page 152: Interrupt Control Mode 2
Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels in mask control.
Page 153 Section 5 Interrupt Controller Program execution state Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 or below? Level 1 interrupt? Mask level 5 or below? Mask level 0? Save PC, CCR, and EXR Pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine...
Page 154: Interrupt Exception Handling Sequence
Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on- chip memory.
Page 155: Interrupt Response Times
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times – the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in on- chip ROM and the stack area in on-chip RAM enables high-speed processing.
Page 156: Dmac Activation By Interrupt
Section 5 Interrupt Controller Table 5.5 Number of Execution States in Interrupt Handling Routine Object of Access External Device 8-Bit Bus 16-Bit Bus 32-Bit Bus On-Chip 2-State 3-State 2-State 3-State 2-State 3-State Symbol Memory Access Access Access Access Access Access Vector fetch S 12 + 4m 6 + 2m...
Page 157: Table 5.6 Interrupt Source Selection And Clear Control
Section 5 Interrupt Controller Selection of Interrupt Sources The activation source for each DMAC channel is selected by DMRSR. The selected activation source is input to the DMAC through the select circuit. When transfer by an on-chip module interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC and cannot be used as a CPU interrupt source.
Page 158: Cpu Priority Control Function Over Dmac
Section 5 Interrupt Controller CPU Priority Control Function Over DMAC The interrupt controller has a function to control the priority among the DMAC and the CPU by assigning priority levels to the DMAC and CPU. Since the priority level can automatically be assigned to the CPU on an interrupt occurrence, it is possible to execute the CPU interrupt exception handling prior to the DMAC transfer.
Page 159: Table 5.7 Cpu Priority Control
Section 5 Interrupt Controller Table 5.7 CPU Priority Control Control Status Interrupt Control Interrupt Interrupt IPSETE in Updating of CPUP2 Mode Priority Mask Bit CPUPCR CPUP2 to CPUP0 to CPUP0 Default I = any B'111 to B'000 Enabled I = 0 B'000 Disabled I = 1...
Page 160: Usage Notes
Section 5 Interrupt Controller Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 161: Instructions That Disable Interrupts
Section 5 Interrupt Controller 5.8.2 Instructions that Disable Interrupts Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 162: Interrupt Flags Of Peripheral Modules
Section 5 Interrupt Controller 5.8.6 Interrupt Flags of Peripheral Modules To clear an interrupt request flag of a peripheral module by the CPU, the flag must be read from after being cleared within the interrupt handling routine even if the peripheral module clock is not generated by dividing the system clock.
Page 163: Section 6 Bus Controller (Bsc)
Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that has a bus arbitration function and controls the operation of the internal bus masters; CPU and DMAC. Features • Write data buffer function Write access to an on-chip peripheral module and access to the on-chip memory can be performed in parallel.
Page 164: Register Descriptions
Section 6 Bus Controller (BSC) Register Descriptions The bus controller has the following registers. • Bus control register 2 (BCR2) 6.2.1 Bus Control Register 2 (BCR2) BCR2 is used for bus arbitration control of the CPU and DMAC, and enabling/disabling of the write data buffer function to the peripheral device.
Page 165: Bus Configuration
Section 6 Bus Controller (BSC) Bus Configuration Figure 6.2 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following two types. • Internal system bus 1 A bus that connects the CPU, DMAC, on-chip ROM, on-chip RAM, and internal peripheral bus.
Page 166: Multi-Clock Function
Section 6 Bus Controller (BSC) Multi-Clock Function The internal functions of this LSI operate synchronously with the system clock (Iφ) or the peripheral module clock (Pφ). Table 6.1 shows the synchronization clock and their corresponding functions. Table 6.1 Synchronization Clocks and Their Corresponding Functions Synchronization Clock Function Name Iφ...
Page 167: Internal Bus
Section 6 Bus Controller (BSC) Internal Bus 6.5.1 Access to Internal Address Space The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space and register space for the on-chip peripheral modules. The number of cycles necessary for access differs according the space.
Page 168: Write Data Buffer Function
Section 6 Bus Controller (BSC) Write Data Buffer Function 6.6.1 Write Data Buffer Function for Peripheral Module This LSI has a write data buffer function for the peripheral module. Using the write data buffer function enables external writes and on-chip memory accesses in parallel. The write data buffer function is made available by setting the PWDBE bit in BCR2 to 1.
Page 169: Bus Arbitration
Section 6 Bus Controller (BSC) Bus Arbitration This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). The internal bus arbiter handles the CPU and DMAC accesses. The bus arbiters decide priority at the prescribed timing, and permit use of the bus by means of the bus request acknowledge signal.
Page 170: Bus Controller Operation In Reset
Section 6 Bus Controller (BSC) • Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS instruction. (In the block transfer instructions, the bus can be transferred in the write cycle and the following transfer data read cycle.) •...
Page 171: Section 7 Dma Controller (Dmac)
Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI includes a 4-channel DMA controller (DMAC). Features • Maximum of 4-G byte address space can be accessed • Byte, word, or longword can be set as data transfer unit •...
Page 172 Section 7 DMA Controller (DMAC) • Address update can be selected from fixed address, offset addition, and increment or decrement by 1, 2, or 4 Address update by offset addition enables to transfer data at addresses which are not placed continuously •...
Page 173: Figure 7.1 Block Diagram Of Dmac
Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1. Internal data bus Internal address bus External pins DREQn* Data buffer DACKn* TENDn* Controller Address buffer Interrupt signals requested to the Operation unit CPU by each channel Operation unit Internal activation sources...
Page 174: Register Descriptions
Section 7 DMA Controller (DMAC) Register Descriptions The DMAC has the following registers. Channel 0 • DMA source address register_0 (DSAR_0) • DMA destination address register_0 (DDAR_0) • DMA offset register_0 (DOFR_0) • DMA transfer count register_0 (DTCR_0) • DMA block size register_0 (DBSR_0) •...
Page 175: Dma Source Address Register (Dsar)
Section 7 DMA Controller (DMAC) Channel 3 • DMA source address register_3 (DSAR_3) • DMA destination address register_3 (DDAR_3) • DMA offset register_3 (DOFR_3) • DMA transfer count register_3 (DTCR_3) • DMA block size register_3 (DBSR_3) • DMA mode control register_3 (DMDR_3) •...
Page 176: Dma Destination Address Register (Ddar)
Section 7 DMA Controller (DMAC) 7.2.2 DMA Destination Address Register (DDAR) DDAR is a 32-bit readable/writable register that specifies the transfer destination address. DDAR updates the transfer destination address every time data is transferred. When DSAR is specified as the source address (the DIRS bit in DACR is 0) in single address mode, DDAR is ignored. Although DDAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred.
Page 177: Dma Offset Register (Dofr)
Section 7 DMA Controller (DMAC) 7.2.3 DMA Offset Register (DOFR) DOFR is a 32-bit readable/writable register that specifies the offset to update the source and destination addresses. Although different values are specified for individual channels, the same values must be specified for the source and destination sides of a single channel. Bit Name Initial Value Bit Name...
Page 178: Dma Transfer Count Register (Dtcr)
Section 7 DMA Controller (DMAC) 7.2.4 DMA Transfer Count Register (DTCR) DTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total transfer size). To transfer 1-byte data in total, set H'00000001 in DTCR. When H'00000000 is set in this register, it means that the total transfer size is not specified and data is transferred with the transfer counter stopped (free running mode).
Page 179: Dma Block Size Register (Dbsr)
Section 7 DMA Controller (DMAC) 7.2.5 DMA Block Size Register (DBSR) DBSR specifies the repeat size or block size. DBSR is enabled in repeat transfer mode and block transfer mode and is disabled in normal transfer mode. Bit Name BKSZH31 BKSZH30 BKSZH29 BKSZH28...
Page 180: Dma Mode Control Register (Dmdr)
Section 7 DMA Controller (DMAC) Table 7.1 Data Access Size, Valid Bits, and Settable Size Settable Size Mode Data Access Size BKSZH Valid Bits BKSZ Valid Bits (Byte) Repeat transfer Byte 31 to 16 15 to 0 1 to 65,536 and block transfer Word 2 to 131,072...
Page 181 Section 7 DMA Controller (DMAC) • DMDR_1 to DMDR_3 Bit Name DACKE TENDE — DREQS — — Initial Value Bit Name — — — — — ESIF DTIF Initial Value R/(W)* R/(W)* Bit Name DTSZ1 DTSZ0 MDS1 MDS0 TSEIE — ESIE DTIE Initial Value...
Page 182 Section 7 DMA Controller (DMAC) Initial Bit Name Value Description Data Transfer Enable Enables/disables a data transfer for the corresponding channel. When this bit is set to 1, it indicates that the DMAC is in operation. Setting this bit to 1 starts a transfer when the auto- request is selected.
Page 183 Section 7 DMA Controller (DMAC) Initial Bit Name Value Description DACK Signal Output Enable DACKE Enables/disables the DACK signal output in single address mode. This bit is ignored in dual address mode. 0: Enables DACK signal output 1: Disables DACK signal output TEND Signal Output Enable TENDE Enables/disables the TEND signal output.
Page 184 Section 7 DMA Controller (DMAC) Initial Bit Name Value Description ERRF R/(W)* System Error Flag Indicates that an address error or an NMI interrupt has been generated. This bit is available only in DMDR_0. Setting this bit to 1 prohibits writing to the DTE bit for all the channels.
Page 185 Section 7 DMA Controller (DMAC) Initial Bit Name Value Description DTIF R/(W)* Data Transfer Interrupt Flag Indicates that a transfer end interrupt by the transfer counter has been requested. 0: A transfer end interrupt by the transfer counter has not been requested 1: A transfer end interrupt by the transfer counter has been requested [Clearing conditions]...
Page 186 Section 7 DMA Controller (DMAC) Initial Bit Name Value Description TSEIE Transfer Size Error Interrupt Enable Enables/disables a transfer size error interrupt. When the next transfer is requested while this bit is set to 1 and the contents of the transfer counter is less than the size of data to be transferred at a single transfer request, the DTE bit is cleared to 0.
Page 187 Section 7 DMA Controller (DMAC) Initial Bit Name Value Description DTF1 Data Transfer Factor 1 and 0 DTF0 Select a DMAC activation source. When the on-chip peripheral module setting is selected, the interrupt source should be selected by DMRSR. When the external request setting is selected, the sampling method should be selected by the DREQS bit.
Page 188 Section 7 DMA Controller (DMAC) Initial Bit Name Value Description DMAP2 DMA Priority Level 2 to 0 DMAP1 Select the priority level of the DMAC. When the CPU has priority over the DMAC, the DMAC masks a transfer DMAP0 request and waits for the timing when the CPU priority becomes lower than the DMAC priority.
Page 189: Dma Address Control Register (Dacr)
Section 7 DMA Controller (DMAC) 7.2.7 DMA Address Control Register (DACR) DACR specifies the operating mode and transfer method. Bit Name DIRS — — — RPTIE ARS1 ARS0 Initial Value Bit Name — — SAT1 SAT0 — — DAT1 DAT0 Initial Value Bit Name SARIE...
Page 190 Section 7 DMA Controller (DMAC) Initial Bit Name Value Description RPTIE Repeat Size End Interrupt Enable Enables/disables a repeat size end interrupt request. In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat-size data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0.
Page 191 Section 7 DMA Controller (DMAC) Initial Bit Name Value Description  19, 18 All 0 Reserved These are read-only bits and cannot be modified. DAT1 Destination Address Update Mode 1 and 0 DAT0 Select the update method of the destination address (DDAR).
Page 192 Section 7 DMA Controller (DMAC) Initial Bit Name Value Description SARA4 Source Address Extended Repeat Area SARA3 Specify the extended repeat area on the source address (DSAR). With the extended repeat area, the specified SARA2 lower address bits are updated and the remaining upper SARA1 address bits are fixed.
Page 193 Section 7 DMA Controller (DMAC) Initial Bit Name Value Description DARA4 Destination Address Extended Repeat Area DARA3 Specify the extended repeat area on the destination address (DDAR). With the extended repeat area, the DARA2 specified lower address bits are updated and the DARA1 remaining upper address bits are fixed.
Page 194: Table 7.2 Settings And Areas Of Extended Repeat Area
Section 7 DMA Controller (DMAC) Table 7.2 Settings and Areas of Extended Repeat Area SARA4 to SARA0 or DARA4 to DARA0 Extended Repeat Area 00000 Not specified 00001 2 bytes specified as extended repeat area by the lower 1 bit of the address 00010 4 bytes specified as extended repeat area by the lower 2 bits of the address 00011...
Page 195: Dma Module Request Select Register (Dmrsr)
Section 7 DMA Controller (DMAC) 7.2.8 DMA Module Request Select Register (DMRSR) DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source. The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no interrupt source.
Page 196: Operations
Section 7 DMA Controller (DMAC) When the auto request setting is selected as the activation source, the cycle stealing or burst access can be selected. When the total transfer size is not specified (DTCR = H'00000000), the transfer counter is stopped and the transfer is continued without the limitation of the transfer count. Operations 7.4.1 Address Modes...
Page 197: Figure 7.2 Example Of Signal Timing In Dual Address Mode
Section 7 DMA Controller (DMAC) Figure 7.2 shows an example of the signal timing in dual address mode and figure 7.3 shows the operation in dual address mode. DMA read cycle DMA write cycle Bφ Address bus DSAR DDAR TEND Figure 7.2 Example of Signal Timing in Dual Address Mode Transfer Address T...
Page 198: Figure 7.4 Data Flow In Single Address Mode
Section 7 DMA Controller (DMAC) Single Address Mode In single address mode, data between an external device and an external memory is directly transferred using the DACK pin instead of DSAR or DDAR. A transfer at a time is performed in one bus cycle.
Page 199: Figure 7.5 Example Of Signal Timing In Single Address Mode
Section 7 DMA Controller (DMAC) Transfer from external memory to external device with DACK DMA cycle Bφ Address bus Address for external memory space DSAR RD signal for external memory space DACK Data output by external memory Data bus TEND Transfer from external device with DACK to external memory DMA cycle Bφ...
Page 200: Transfer Modes
Section 7 DMA Controller (DMAC) 7.4.2 Transfer Modes Normal Transfer Mode In normal transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer mode.
Page 201: Figure 7.9 Operations In Repeat Transfer Mode
Section 7 DMA Controller (DMAC) Repeat Transfer Mode In repeat transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. The repeat size can be specified in DBSR up to 65536 ×...
Page 202: Figure 7.10 Operations In Block Transfer Mode
Section 7 DMA Controller (DMAC) Block Transfer Mode In block transfer mode, one block size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as total transfer size by DTCR. The block size can be specified in DBSR up to 65536 ×...
Page 203: Figure 7.11 Operation In Single Address Mode In Block Transfer Mode (Block Area Specified)
Section 7 DMA Controller (DMAC) Address T Transfer DACK Block BKSZH × data access size Address B Figure 7.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified) Address T Address T Transfer First block First block BKSZH ×...
Page 204: Activation Sources
Section 7 DMA Controller (DMAC) 7.4.3 Activation Sources The DMAC is activated by an auto request, an on-chip module interrupt, and an external request. The activation source is specified by bits DTF1 and DTF0 in DMDR. Activation by Auto Request The auto request activation is used when a transfer request from an external device or an on-chip peripheral module is not generated such as a transfer between memory and memory or between memory and an on-chip peripheral module which does not request a transfer.
Page 205: Table 7.4 List Of On-Chip Module Interrupts To Dmac
Section 7 DMA Controller (DMAC) Table 7.4 List of On-chip module interrupts to DMAC DMRSR On-Chip (Vector Module Number) On-Chip Module Interrupt Source ADI0 (A/D conversion end interrupt) A/D_0 ADI1 (A/D conversion end interrupt) A/D_1 TGI0A (TGI0A input capture/compare match) TPU_0 TGI1A (TGI1A input capture/compare match) TPU_1...
Page 206: Bus Access Modes
Section 7 DMA Controller (DMAC) Activation by External Request A transfer is started by a transfer request signal (DREQ) from an external device. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by the DREQ assertion. A transfer request signal is input to the DREQ pin.
Page 207: Figure 7.13 Example Of Timing In Cycle Stealing Mode
Section 7 DMA Controller (DMAC) Figure 7.13 shows an example of timing in cycle stealing mode. The transfer conditions are as follows: • Address mode: Single address mode • Sampling method of the DREQ signal: Low level detection DREQ Bus cycle DMAC DMAC Bus released temporarily for the CPU...
Page 208: Extended Repeat Area Function
Section 7 DMA Controller (DMAC) 7.4.5 Extended Repeat Area Function The source and destination address sides can be specified as the extended repeat area. The contents of the address register repeat addresses within the area specified as the extended repeat area. For example, to use a ring buffer as the transfer target, the contents of the address register should return to the start address of the buffer every time the contents reach the end address of the buffer (overflow on the ring buffer address).
Page 209: Figure 7.15 Example Of Extended Repeat Area Operation
Section 7 DMA Controller (DMAC) When the area represented by the lower three bits of DSAR (eight bytes) is specified as the extended repeat area (SARA4 to SARA0 = B'00011) External memory Area specified by DSAR H'23FFFE H'23FFFF H'240000 H'240000 Repeat H'240001 H'240001...
Page 210: Address Update Function Using Offset
Section 7 DMA Controller (DMAC) 7.4.6 Address Update Function using Offset The source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or offset addition. When the offset addition is selected, the offset specified by the offset register (DOFR) is added to the address every time the DMAC transfers the data access size of data.
Page 211: Figure 7.18 Operation Of Offset Addition
Section 7 DMA Controller (DMAC) The address is calculated by the offset set in DOFR and the contents of DSAR and DDAR. Although the DMAC calculates only addition, an offset subtraction can be realized by setting the negative value in DOFR. In this case, the negative value must be 2's complement. Basic Transfer Using Offset Figure 7.18 shows a basic operation of a transfer using the offset addition.
Page 212: Figure 7.19 Xy Conversion Operation Using Offset Addition In Repeat Transfer Mode
Section 7 DMA Controller (DMAC) XY Conversion Using Offset Figure 7.19 shows the XY conversion using the offset addition in repeat transfer mode. Data 1 Data 1 Data 9 Data 2 Data 5 Data 13 Data 3 1st transfer Data 4 Data 2 Data 10 Data 5...
Page 213: Figure 7.20 Xy Conversion Flowchart Using Offset Addition In Repeat Transfer Mode
Section 7 DMA Controller (DMAC) Figure 7.29 shows a flowchart of the XY conversion. Start Set address and transfer count Set repeat transfer mode Enable repeat escape interrupt Set DTE bit to 1 Receives transfer request Transfers data Repeat size = 0? Decrements transfer count and repeat size Initializes transfer source address...
Page 214: Register During Dma Transfer
Section 7 DMA Controller (DMAC) 7.4.7 Register during DMA Transfer The DMAC registers are updated by a DMA transfer. The value to be updated differs according to the other settings and transfer state. The registers to be updated are DSAR, DDAR, DTCR, bits BKSZH and BKSZ in DBSR, and the DTE, ACT, ERRF, ESIF, and DTIF bits in DMDR.
Page 215 Section 7 DMA Controller (DMAC) DMA Destination Address Register When the transfer destination address set in DDAR is accessed, the contents of DDAR are output and then are updated to the next address. The increment or decrement can be specified by bits DAT1 and DAT0 in DACR. When DAT1 and DAT0 = B'00, the address is fixed.
Page 216 Section 7 DMA Controller (DMAC) While data is being transferred, all the bits of DTCR may be changed. DTCR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DTCR during the transfer may be updated regardless of the access by the CPU.
Page 217: Figure 7.21 Procedure For Changing Register Setting For Channel Being Transferred
Section 7 DMA Controller (DMAC) Writing to the registers for the channels when the corresponding DTE bit is set to 1 is prohibited (except for the DTE bit). When changing the register settings after writing 0 to the DTE bit, confirm that the DTE bit has been cleared to 0.
Page 218 Section 7 DMA Controller (DMAC) ERRF Bit in DMDR When an address error or an NMI interrupt occur, the DMAC clears the DTE bits for all the channels to stop a transfer. In addition, it sets the ERRF bit in DMDR_0 to 1 to indicate that an address error or an NMI interrupt has occurred regardless of whether or not the DMAC is in operation.
Page 219: Priority Of Channels
Section 7 DMA Controller (DMAC) 7.4.8 Priority of Channels The channels of the DMAC are given following priority levels: channel 0 > channel 1 > channel 2 > channel3. Table 7.5 shows the priority levels among the DMAC channels. Table 7.5 Priority among DMAC Channels Channel Priority...
Page 220: Dma Basic Bus Cycle
Section 7 DMA Controller (DMAC) 7.4.9 DMA Basic Bus Cycle Figure 7.23 shows an examples of signal timing of a basic bus cycle. In figure 7.23, data is transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When the bus mastership is passed from the DMAC to the CPU, data is read from the source address and it is written to the destination address.
Page 221: Bus Cycles In Dual Address Mode
Section 7 DMA Controller (DMAC) 7.4.10 Bus Cycles in Dual Address Mode Normal Transfer Mode (Cycle Stealing Mode) In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one word, or one longword) is completed. One bus cycle or more by the CPU are executed in the bus released cycles.
Page 222: Figure 7.25 Example Of Transfer In Normal Transfer Mode By Cycle Stealing (Transfer Source Dsar = Odd Address And Source Address Increment)
Section 7 DMA Controller (DMAC) DMA byte DMA word DMA byte DMA word DMA word DMA byte DMA word DMA byte DMA word DMA word read cycle read cycle read cycle write cycle write cycle read cycle read cycle read cycle write cycle write cycle Bφ...
Page 223: Figure 7.27 Example Of Transfer In Normal Transfer Mode By Burst Access
Section 7 DMA Controller (DMAC) Normal Transfer Mode (Burst Mode) In burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. When a burst transfer starts, a transfer request from a channel having priority is suspended until the burst transfer is completed.
Page 224: Figure 7.28 Example Of Transfer In Block Transfer Mode
Section 7 DMA Controller (DMAC) Block Transfer Mode In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer request is completed. In figure 7.28, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer mode.
Page 225: Figure 7.29 Example Of Transfer In Normal Transfer Mode Activated By Dreq Falling Edge
Section 7 DMA Controller (DMAC) Activation Timing by DREQ Falling Edge Figure 7.29 shows an example of normal transfer mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle.
Page 226: Figure 7.30 Example Of Transfer In Normal Transfer Mode Activated By Dreq Low Level
Section 7 DMA Controller (DMAC) Activation Timing by DREQ Low Level Figure 7.30 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle.
Page 227: Figure 7.31 Example Of Transfer In Block Transfer Mode Activated By Dreq Low Level
Section 7 DMA Controller (DMAC) Figure 7.31 shows an example of block transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC.
Page 228: Figure 7.32 Example Of Transfer In Normal Transfer Mode Activated
Section 7 DMA Controller (DMAC) Activation Timing by DREQ Low Level with NRD = 1 When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 7.32 shows an example of normal transfer mode activated by the DREQ signal low level with NRD = 1.
Page 229: Bus Cycles In Single Address Mode
Section 7 DMA Controller (DMAC) 7.4.11 Bus Cycles in Single Address Mode Single Address Mode (Read and Cycle Stealing) In single address mode, one byte, one word, or one longword of data is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU are executed in the bus released cycles.
Page 230: Figure 7.34 Example Of Transfer In Single Address Mode (Byte Write)
Section 7 DMA Controller (DMAC) Single Address Mode (Write and Cycle Stealing) In single address mode, data of one byte, one word, or one longword is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU are executed in the bus released cycles.
Page 231: Figure 7.35 Example Of Transfer In Single Address Mode Activated By Dreq Falling Edge
Section 7 DMA Controller (DMAC) Activation Timing by DREQ Falling Edge Figure 7.35 shows an example of single address mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle.
Page 232: Figure 7.36 Example Of Transfer In Single Address Mode Activated By Dreq Low Level
Section 7 DMA Controller (DMAC) Activation Timing by DREQ Low Level Figure 7.36 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle.
Page 233: Figure 7.37 Example Of Transfer In Single Address Mode Activated By Dreq Low Level With Nrd = 1
Section 7 DMA Controller (DMAC) Activation Timing by DREQ Low Level with NRD = 1 When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 7.37 shows an example of single address mode activated by the DREQ signal low level with NRD = 1.
Page 234: Dma Transfer End
Section 7 DMA Controller (DMAC) DMA Transfer End Operations on completion of a transfer differ according to the transfer end condition. DMA transfer completion is indicated that the DTE and ACT bits in DMDR are changed from 1 to 0. Transfer End by DTCR Change from 1, 2, or 4, to 0 When DTCR is changed from 1, 2, or 4 to 0, a DMA transfer for the channel is completed.
Page 235 Section 7 DMA Controller (DMAC) Transfer End by Interrupt on Extended Repeat Area Overflow When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area overflow is requested.
Page 236: Relationship Among Dmac And Other Bus Masters
Section 7 DMA Controller (DMAC) Transfer End by Address Error When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is forced to stop.
Page 237: Bus Arbitration Among Dmac And Other Bus Masters
Section 7 DMA Controller (DMAC) 7.6.2 Bus Arbitration among DMAC and Other Bus Masters When DMA transfer cycles are consecutively performed, bus cycles of other bus masters may be inserted between the transfer cycles. The DMAC can release the bus temporarily to pass the bus to other bus masters.
Page 238: Interrupt Sources
Section 7 DMA Controller (DMAC) Interrupt Sources The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer escape end interrupt which is generated when a transfer is terminated before the transfer counter reaches 0. Table 7.6 shows interrupt sources and priority. Table 7.6 Interrupt Sources and Priority Abbr.
Page 239 Section 7 DMA Controller (DMAC) Each interrupt source is specified by the interrupt enable bit in the register for the corresponding channel. A transfer end interrupt by the transfer counter, a transfer size error interrupt, a repeat size end interrupt, an interrupt by an extended repeat area overflow on the source address, and an interrupt by an extended repeat area overflow on the destination address are enabled or disabled by the DTIE bit in DMDR, the TSEIE bit in DMDR, the RPTIE bit in DACR, SARIE bit in DACR, and the DARIE bit in DACR, respectively.
Page 240: Figure 7.38 Interrupt And Interrupt Sources
Section 7 DMA Controller (DMAC) TSIE bit DTIE bit Transfer end DMAC is activated in interrupt DTIF bit transfer size error state RPTIE bit [Setting condition] DMAC is activated When DTCR becomes 0 after BKSZ bits are and transfer ends changed from 1 to 0 SARIE bit ESIE bit...
Page 241: Notes On Usage
Section 7 DMA Controller (DMAC) Notes on Usage 1. DMAC Register Access During Operation Except for clearing the DTE bit in DMDR, the settings for channels being transferred (including waiting state) must not be changed. The register settings must be changed during the transfer prohibited state.
Page 242 Section 7 DMA Controller (DMAC) Rev. 3.00 Mar. 14, 2006 Page 204 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 243: Section 8 I/O Ports
Section 8 I/O Ports Section 8 I/O Ports Table 8.1 summarizes the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or external interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and an input buffer control register (ICR) that controls input buffer on/off.
Page 244 Section 8 I/O Ports Function Input Open- Schmitt- Pull-up Drain Trigger Output Port Description Input Output Input * Function Function   Port 2 General I/O port P23/ TIOCC3/ P23, IRQ11-A also functioning TIOCD3 TIOCC3, as interrupt inputs, TIOCD3, IRQ11-A TPU I/Os* , and SSU I/Os...
Page 245 Section 8 I/O Ports Function Input Open- Schmitt- Pull-up Drain Trigger Output Port Description Input Output Input * Function Function      Port 4 General I/O port P47/AN11 also functioning   P46/AN10 as A/D converter  ...
Page 246 Section 8 I/O Ports Function Input Open- Schmitt- Pull-up Drain Trigger Output Port Description Input Output Input * Function Function    Port D General I/O port PD7/SCS1 also functioning PD6/SSCK1   Only for as SSU I/Os  ...
Page 247 Section 8 I/O Ports Function Input Open- Schmitt- Pull-up Drain Trigger Output Port Description Input Output Input * Function Function   Port J General I/O port PJ1/ TIOCA6 PJ1, also functioning TIOCB6 TIOCA6, as TPU I/Os TIOCB6   PJ0/ PJ0, TIOCA6...
Page 248: Register Descriptions
Section 8 I/O Ports Register Descriptions Table 8.2 lists each port registers. Table 8.2 Register Configuration in Each Port Registers Number of Port Pins PORT PHRTIDR    Port 1   Port 2*    Port 3 ...
Page 249: Figure 8.1 Port Block Diagram
Section 8 I/O Ports Figure 8.1 is a port block diagram. Address output Data output On-chip peripheral module output WPCR RPCR WDDR On-chip peripheral module output enable On-chip peripheral module output signal WODR RODR RPOR To on-chip Input buffer Peripheral module RPOR [Legend] WICR...
Page 250: Data Direction Register (Pnddr) (N = 1 To 3, 6, A, D, H, J, And K)
Section 8 I/O Ports 8.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D, H, J, and K) DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from the DDR is invalid and DDR is always read as an undefined value.
Page 251: Port Register (Portn) (N = 1 To 6, A, D, H, J, And K)
Section 8 I/O Ports 8.1.3 Port Register (PORTn) (n = 1 to 6, A, D, H, J, and K) PORT is an 8-bit read-only register that reflects the port pin status. A write to PORT is invalid. When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the ICR value.
Page 252: Pull-Up Mos Control Register (Pnpcr) (N = D, H, J, And K)
Section 8 I/O Ports Bit Name Pn7ICR Pn6ICR Pn5ICR Pn4ICR Pn3ICR Pn2ICR Pn1ICR Pn0ICR Initial Value Note: The lower four bits are valid and the upper four bits are reserved for port 2 input buffer control register (P2ICR). The lower seven bits are valid and the upper one bit is reserved for port 6 input buffer control register (P6ICR). The upper seven bits are valid and the lower one bit is reserved for port A input buffer control register (PAICR).
Page 253: Open-Drain Control Register (Pnodr) (N = 2)
Section 8 I/O Ports 8.1.6 Open-Drain Control Register (PnODR) (n = 2) ODR is an 8-bit readable/writable register that selects the open-drain output function. If a bit in ODR is set to 1, the pin corresponding to that bit in ODR functions as an NMOS open- drain output.
Page 254: Output Buffer Control
Section 8 I/O Ports Output Buffer Control This section describes the output priority of each pin. The name of each peripheral module pin is followed by "_OE". This (for example: MIOCA4_OE) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0).
Page 255 Section 8 I/O Ports P15/RxD3/IRQ5 The pin function is switched as shown below according to the P15DDR bit setting. Setting I/O Port Module Name Pin Function P15DDR I/O port P15 output P15 input (initial setting) 0 P14/TxD3/IRQ4 The pin function is switched as shown below according to the combination of the SCI_3 and P14DDR bit settings.
Page 256 Section 8 I/O Ports P12/IRQ2 The pin function is switched as shown below according to the P12DDR bit setting. Setting I/O Port Module Name Pin Function P12DDR I/O port P12 output P12 input (initial setting) 0 P11/IRQ1 The pin function is switched as shown below according to the P11DDR bit setting. Setting I/O Port Module Name...
Page 257: Port 2
Section 8 I/O Ports 8.2.2 Port 2 P23/TIOCC3/TIOCD3/IRQ11-A The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_3, and P23DDR bit settings. Setting TPU_3* I/O Port Module Name Pin Function TIOCD3_OE P23DDR ...
Page 258 Section 8 I/O Ports P21/TIOCA3/IRQ9-A/SCS2 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), SSU_2, TPU_3, and P21DDR bit settings. Setting SSU_2 TPU_3* I/O Port SCS2_OE Module Name Pin Function TIOCA3_OE P21DDR SCS2 output...
Page 259: Port 3
Section 8 I/O Ports 8.2.3 Port 3 P37/PO15/TIOCA2/TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_2, PPG, and P37DDR bit settings. Setting TPU_2* PPG* I/O Port Module Name Pin Function TIOCB2_OE PO15_OE...
Page 260 Section 8 I/O Ports P35/PO13/TIOCA1/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_1, PPG, and P35DDR bit settings. Setting TPU_1* PPG* I/O Port Module Name Pin Function TIOCB1_OE PO13_OE P35DDR...
Page 261 Section 8 I/O Ports P33/PO11/TIOCC0/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P33DDR bit settings. Setting TPU_0* PPG* I/O Port Module Name Pin Function TIOCD0_OE PO11_OE P33DDR...
Page 262 Section 8 I/O Ports P31/PO9/TIOCA0/TIOCB0 The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P31DDR bit settings. Setting TPU_0* PPG* I/O Port Module Name Pin Function TIOCB0_OE PO9_OE P31DDR...
Page 263: Port 6
Section 8 I/O Ports 8.2.4 Port 6 P66/IRQ14 The pin function is switched as shown below according to the P66DDR bit setting. Setting I/O Port Module Name Pin Function P66DDR I/O port P66 output P66 input (initial setting) P65/IRQ13/HRxD The pin function is switched as shown below according to the P65DDR bit setting. Setting I/O Port Module Name...
Page 264 Section 8 I/O Ports P63/IRQ11-B The pin function is switched as shown below according to the P63DDR bit setting. Setting I/O Port Module Name Pin Function P63DDR I/O port P63 output P63 input (initial setting) 0 P62/SCK4/IRQ10-B The pin function is switched as shown below according to the combination of the SCI_4 and P62DDR bit settings.
Page 265: Port A
Section 8 I/O Ports P60/TxD4/IRQ8-B The pin function is switched as shown below according to the combination of the SCI_4 and P60DDR bit settings. Setting SCI_4 I/O Port Module Name Pin Function TxD4_OE P60DDR  SCI_4 TxD4 output I/O port P60 output P60 input (initial setting) 8.2.5...
Page 266 Section 8 I/O Ports The pin function is switched as shown below according to the PA5DDR bit setting. Setting I/O Port Module Name Pin Function PA5DDR I/O port PA5 output PA5 input (initial setting) The pin function is switched as shown below according to the PA4DDR bit setting. Setting I/O Port Module Name...
Page 267 Section 8 I/O Ports PA2/SSI2 The pin function is switched as shown below according to the combination of the SSU_2 and the PA2DDR bit settings. Setting SSU_2 I/O Port Module Name Pin Function SSI2_OE PA2DDR  SSU_2 SSI2 output I/O port PA2 output PA2 input (initial setting) PA1/SSCK2...
Page 268: Port D
Section 8 I/O Ports 8.2.6 Port D PD7/SCS1 The pin function is switched as shown below according to the combination of the SSU_1 and the PD7DDR bit settings. Setting SSU_2 I/O Port SCS1_OE Module Name Pin Function PD7DDR SCS1 output ...
Page 269 Section 8 I/O Ports PD4/SSO1 The pin function is switched as shown below according to the combination of the SSU_1 and the PD4DDR bit settings. Setting SSU_1 I/O Port Module Name Pin Function SSO1_OE PD4DDR  SSU_1 SSO1 output I/O port PD4 output PD4 input (initial setting) PD3/SCS0...
Page 270 Section 8 I/O Ports PD1/SSI0 The pin function is switched as shown below according to the combination of the SSU_0 and the PD1DDR bit settings. Setting SSU_0 I/O Port Module Name Pin Function SSI0_OE PD1DDR  SSU_0 SSI0 output I/O port PD1 output PD1 input (initial setting) PD0/SSO0...
Page 271: Port H
Section 8 I/O Ports 8.2.7 Port H PH7, PH6, PH5, PH4, PH3, PH2, PH1, and PH0 Port H functions as an 8-bit I/O port and also functions as a realtime input port. Using port H as the realtime input port, the pin status of port H is stored in PHRTIDR by the following triggers a low level, a falling edge, a rising edge, or both edges of pin IRQ14.
Page 272 Section 8 I/O Ports PJ6/TIOCA8 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_8, and PJ6DDR bit settings. Setting TPU_8 I/O Port Module Name Pin Function TIOCA8_OE PJ6DDR ...
Page 273 Section 8 I/O Ports PJ3/TIOCC6/TIOCD6/TCLKF The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ3DDR bit settings. Setting TPU_6 I/O Port Module Name Pin Function TIOCD6_OE PJ3DDR ...
Page 274: Port K
Section 8 I/O Ports PJ0/TIOCA6 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ0DDR bit settings. Setting TPU_6 I/O Port Module Name Pin Function TIOCA6_OE PJ0DDR ...
Page 275 Section 8 I/O Ports PK5/TIOCA10/TIOCB10 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_10, and PK5DDR bit settings. Setting TPU_10 I/O Port Module Name Pin Function TIOCB10_OE PK5DDR ...
Page 276 Section 8 I/O Ports PK2/TIOCC9 The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK2DDR bit settings. Setting TPU_9 I/O Port Module Name Pin Function TIOCC9_OE PK2DDR ...
Page 277: Table 8.4 Available Output Signals And Settings In Each Port
Section 8 I/O Ports Table 8.4 Available Output Signals and Settings in Each Port Signal Output Output Selection Specification Signal Register Port Signal Name Name Settings Peripheral Module Settings SCK3_OE SCK3 When SCMR_3.SMIF = 1: SCR_3.TE = 1 or SCR_3.RE = 1 while SMR_3.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR_3.SMIF = 0:...
Page 278 Section 8 I/O Ports Signal Output Output Selection Specification Signal Register Port Signal Name Name Settings Peripheral Module Settings TIOCA0_OE* TIOCA0 TPU.TIORH_0.IOA3 = 0, TPU.TIORH_0.IOA[1,0] = 01/10/11 PO8_OE* NDERH.NDER8 = 1 HTxD_OE HTxD HCAN MBCR.MBCRn = 0, HCAN.TXRP.TXRn = 1 while HCAN.HCANMON.HCANE = 1, HCAN.HCANMON.TxSTP = 0 (n = 1 to 15)
Page 279 Section 8 I/O Ports Signal Output Output Selection Specification Signal Register Port Signal Name Name Settings Peripheral Module Settings SSO1_OE SSO1 When SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 1: SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1 or SSU.SSCRH_1.BIDE = 1, SSU.SSER_1.RE = 0, SSU.SSER_1.TE When SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0: SSU.SSCRH_1.BIDE = 1, SSU.SSER_1.RE = 0, SSU.SSER_1.TE When SSU.SSCRL_1.SSUMS = 1:...
Page 280 Section 8 I/O Ports Signal Output Output Selection Specification Signal Register Port Signal Name Name Settings Peripheral Module Settings TIOCB11_OE TIOCB11 TPU.TIOR_11.IOB3 = 0, TPU.TIOR_11.IOB[1, 0] = 01/10/11 TIOCA11_OE TIOCA11 TPU.TIOR_11.IOA3 = 0, TPU.TIOR_11.IOA[1, 0] = 01/10/11 TIOCB10_OE TIOCB10 TPU.TIOR_10.IOB3 = 0, TPU.TIOR_10.IOB[1, 0] = 01/10/11 TIOCA10_OE TIOCA10...
Page 281: Port Function Controller
Section 8 I/O Ports Port Function Controller The port function controller controls the I/O ports. The port function controller incorporates the following registers. • Port function control register 9 (PFCR9)* • Port function control register A (PFCRA) • Port function control register B (PFCRB) Note: * PFCR9 is supported only by the H8SX/1527.
Page 282 Section 8 I/O Ports Initial Bit Name Value Description TPUMS2 TPU I/O Pin Multiplex Function Select Selects TIOCA2 function 0: Specifies P36 as output compare output and input capture 1: Specifies P37 as input capture input and P36 as output compare TPUMS1 TPU I/O Pin Multiplex Function Select...
Page 283: Port Function Control Register A (Pfcra)
Section 8 I/O Ports 8.3.2 Port Function Control Register A (PFCRA) PFCRA selects the multiple functions for the TPU (unit 1) I/O pins. Bit Name TPUMS11 TPUMS10 TPUMS9A TPUMS9B TPUMS8 TPUMS7 TPUMS6A TPUMS6B Initial Value Initial Bit Name Value Description TPUMS11 0 TPU I/O Pin Multiplex Function Select Selects TIOCA11 function...
Page 284 Section 8 I/O Ports Initial Bit Name Value Description TPUMS8 TPU I/O Pin Multiplex Function Select Selects TIOCA8 function 0: Specifies PJ6 as output compare output and input capture 1: Specifies PJ7 as input capture input and PJ6 as output compare TPUMS7 TPU I/O Pin Multiplex Function Select...
Page 285: Port Function Control Register B (Pfcrb)
Section 8 I/O Ports 8.3.3 Port Function Control Register B (PFCRB) PFCRB selects the input pins for IRQ14 to IRQ8. Bit Name ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 Initial Value Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0.
Page 286 Section 8 I/O Ports Initial Bit Name Value Description IRQ10 Pin Select ITS10 Selects an input pin for IRQ10. 0: Pin P22 is used as IRQ10-A input 1: Pin P62 is used as IRQ10-B input IRQ9 Pin Select ITS9 Selects an input pin for IRQ9. 0: Pin P21 is used as IRQ9-A input 1: Pin P61 is used as IRQ9-B input IRQ8 Pin Select...
Page 287: Usage Notes
Section 8 I/O Ports Usage Notes 8.4.1 Notes on Input Buffer Control Register (ICR) Setting • When the ICR setting is changed, the LSI may malfunction due to an edge occurred internally according to the pin states. To change the ICR setting, fix the pin high or disable the input function corresponding to the pin by setting the on-chip module registers.
Page 288 Section 8 I/O Ports Rev. 3.00 Mar. 14, 2006 Page 250 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 289: Section 9 16-Bit Timer Pulse Unit (Tpu)
Section 9 16-Bit Timer Pulse Unit (TPU) Section 9 16-Bit Timer Pulse Unit (TPU) This LSI has two on-chip 16-bit timer pulse units (TPU): unit 0 and unit1. Each unit comprises six 16-bit timer channels, that is, there are 12 timer channels in total. However, the H8SX/1525 does not include unit 0.
Page 290: Table 9.1 Unit Configuration For Each Product
Section 9 16-Bit Timer Pulse Unit (TPU) Note: * The H8SX/1527 does not have pins TIOCA4, TIOCB4, TIOCA5, and TIOCB5 for channels 4 and 5. Therefore, 0-, 1-, or toggle-output waveform and PWM waveform at an input capture input and a compare match cannot be output. Table 9.1 Unit Configuration for Each Product Product...
Page 291 Section 9 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 PWM mode   Phase counting mode     Buffer operation DMAC activation compare compare compare compare compare compare match or match or...
Page 292: Table 9.3 Tpu Functions (Unit 1)
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.3 TPU Functions (Unit 1) Item Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Count clock Pφ/1 Pφ/1 Pφ/1 Pφ/1 Pφ/1 Pφ/1 Pφ/4 Pφ/4 Pφ/4 Pφ/4 Pφ/4 Pφ/4 Pφ/16 Pφ/16 Pφ/16...
Page 293 Section 9 16-Bit Timer Pulse Unit (TPU) Item Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Interrupt sources 5 sources 4 sources 4 sources 5 sources 4 sources 4 sources Compare Compare Compare Compare Compare Compare match or match or match or...
Page 294: Figure 9.1 Block Diagram Of Tpu (Unit 0)
Section 9 16-Bit Timer Pulse Unit (TPU) Interrupt request signals Channel 3: TGI3A Input/output pins TGI3B Channel 3: TIOCA3 TGI3C TIOCB3 TGI3D TIOCC3 TCI3V TIOCD3 Channel 4: TGI4A Channel 4: TIOCA4* TGI4B TIOCB4* TCI4V Channel 5: TIOCA5* TCI4U TIOCB5* Channel 5: TGI5A TGI5B TCI5V...
Page 295: Figure 9.2 Block Diagram Of Tpu (Unit 1)
Section 9 16-Bit Timer Pulse Unit (TPU) Interrupt request signals Channel 9: TGI9A Input/output pins TGI9B Channel 9: TIOCA9 TGI9C TIOCB9 TGI9D TIOCC9 TCI9V TIOCD9 Channel 10: TGI10A Channel 10: TIOCA10 TGI10B TIOCB10 TCI10V Channel 11: TIOCA11 TCI10U TIOCB11 Channel 11: TGI11A TGI11B TCI11V...
Page 296: Input/Output Pins
Section 9 16-Bit Timer Pulse Unit (TPU) Input/Output Pins Table 9.4 shows TPU pin configurations. Table 9.4 Pin Configuration Unit Channel Symbol Function TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) TCLKB Input External clock B input pin...
Page 297 Section 9 16-Bit Timer Pulse Unit (TPU) Unit Channel Symbol Function TCLKE Input External clock A input pin (Channel 7 and 11 phase counting mode A phase input) TCLKF Input External clock B input pin (Channel 7 and 11 phase counting mode B phase input) TCLKG Input External clock C input pin...
Page 298: Register Descriptions
Section 9 16-Bit Timer Pulse Unit (TPU) Register Descriptions The TPU has the following registers in each channel. The registers for unit 0 and unit 1 have the same functions except bit 7 (TTGE bit for unit 0 and reserved bit for unit 1) in TIER. This section describes unit 0 registers. Unit 0 •...
Page 299 Section 9 16-Bit Timer Pulse Unit (TPU) • Channel 2: Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2) •...
Page 300 Section 9 16-Bit Timer Pulse Unit (TPU) • Channel 5: Timer control register_5 (TCR_5) Timer mode register_5 (TMDR_5) Timer I/O control register_5 (TIOR_5) Timer interrupt enable register_5 (TIER_5) Timer status register_5 (TSR_5) Timer counter_5 (TCNT_5) Timer general register A_5 (TGRA_5) Timer general register B_5 (TGRB_5) •...
Page 301 Section 9 16-Bit Timer Pulse Unit (TPU) • Channel 7: Timer control register_7 (TCR_7) Timer mode register_7 (TMDR_7) Timer I/O control register _7 (TIOR_7) Timer interrupt enable register_7 (TIER_7) Timer status register_7 (TSR_7) Timer counter_7 (TCNT_7) Timer general register A_7 (TGRA_7) Timer general register B_7 (TGRB_7) •...
Page 302 Section 9 16-Bit Timer Pulse Unit (TPU) • Channel 10: Timer control register_10 (TCR_10) Timer mode register_10 (TMDR_10) Timer I/O control register _10 (TIOR_10) Timer interrupt enable register_10 (TIER_10) Timer status register_10 (TSR_10) Timer counter_10 (TCNT_10) Timer general register A_10 (TGRA_10) Timer general register B_10 (TGRB_10) •...
Page 303: Timer Control Register (Tcr)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.1 Timer Control Register (TCR) TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only while TCNT operation is stopped. Bit Name CCLR2 CCLR1...
Page 304: Table 9.5 Cclr2 To Cclr0 (Channels 0 And 3)
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.5 CCLR2 to CCLR0 (Channels 0 and 3) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/...
Page 305: Table 9.7 Input Clock Edge Selection
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.7 Input Clock Edge Selection Clock Edge Selection Input Clock CKEG1 CKEG0 Internal Clock External Clock Counted at falling edge Counted at rising edge Counted at rising edge Counted at falling edge Counted at both edges Counted at both edges [Legend]...
Page 306: Table 9.10 Tpsc2 To Tpsc0 (Channel 2)
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.10 TPSC2 to TPSC0 (Channel 2) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input...
Page 307: Table 9.12 Tpsc2 To Tpsc0 (Channel 4)
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.12 TPSC2 to TPSC0 (Channel 4) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input...
Page 308: Timer Mode Register (Tmdr)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.2 Timer Mode Register (TMDR) TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only while TCNT operation is stopped. Bit Name Initial Value Initial...
Page 309: Table 9.14 Md3 To Md0
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.14 MD3 to MD0 Bit 3 Bit 2 Bit 1 Bit 0 MD3* MD2* Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ...
Page 310: Timer I/O Control Register (Tior)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.3 Timer I/O Control Register (TIOR) TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0).
Page 311 Section 9 16-Bit Timer Pulse Unit (TPU) • TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Initial Bit Name Value Description IOB3 I/O Control B3 to B0 IOB2 Specify the function of TGRB. IOB1 For details, see tables 9.15, 9.17, 9.18, 9.19, 9.21, and 9.22.
Page 312: Table 9.15 Tiorh_0
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.15 TIORH_0 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_0 IOB3 IOB2 IOB1 IOB0 Function TIOCB0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 313: Table 9.16 Tiorl_0
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.16 TIORL_0 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_0 IOD3 IOD2 IOD1 IOD0 Function TIOCD0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 314: Table 9.17 Tior_1
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.17 TIOR_1 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_1 IOB3 IOB2 IOB1 IOB0 Function TIOCB1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 315: Table 9.18 Tior_2
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.18 TIOR_2 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_2 IOB3 IOB2 IOB1 IOB0 Function TIOCB2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 316: Table 9.19 Tiorh_3
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.19 TIORH_3 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_3 IOB3 IOB2 IOB1 IOB0 Function TIOCB3 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 317: Table 9.20 Tiorl_3
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.20 TIORL_3 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_3 IOD3 IOD2 IOD1 IOD0 Function TIOCD3 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 318: Table 9.21 Tior_4
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.21 TIOR_4 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_4 IOB3 IOB2 IOB1 IOB0 Function TIOCB4 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 319: Table 9.22 Tior_5
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.22 TIOR_5 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_5 IOB3 IOB2 IOB1 IOB0 Function TIOCB5 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 320: Table 9.23 Tiorh_0
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.23 TIORH_0 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 IOA3 IOA2 IOA1 IOA0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 321: Table 9.24 Tiorl_0
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.24 TIORL_0 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_0 IOC3 IOC2 IOC1 IOC0 Function TIOCC0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 322: Table 9.25 Tior_1
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.25 TIOR_1 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_1 IOA3 IOA2 IOA1 IOA0 Function TIOCA1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 323: Table 9.26 Tior_2
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.26 TIOR_2 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_2 IOA3 IOA2 IOA1 IOA0 Function TIOCA2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 324: Table 9.27 Tiorh_3
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.27 TIORH_3 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_3 IOA3 IOA2 IOA1 IOA0 Function TIOCA3 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 325: Table 9.28 Tiorl_3
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.28 TIORL_3 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_3 IOC3 IOC2 IOC1 IOC0 Function TIOCC3 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 326: Table 9.29 Tior_4
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.29 TIOR_4 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_4 IOA3 IOA2 IOA1 IOA0 Function TIOCA4 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 327: Table 9.30 Tior_5
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.30 TIOR_5 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_5 IOA3 IOA2 IOA1 IOA0 Function TIOCA5 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 328: Timer Interrupt Enable Register (Tier)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.4 Timer Interrupt Enable Register (TIER) TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Name TTGE* — TCIEU TCIEV TGIED TGIEC TGIEB...
Page 329 Section 9 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGIED TGR Interrupt Enable D Enables/disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved.
Page 330: Timer Status Register (Tsr)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.5 Timer Status Register (TSR) TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel. Bit Name TCFD — TCFU TCFV TGFD TGFC TGFB TGFA Initial Value R/(W)* R/(W)* R/(W)*...
Page 331 Section 9 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TCFV R/(W)* Overflow Flag Status flag that indicates that a TCNT overflow has occurred. [Setting condition] • When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition] •...
Page 332 Section 9 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGFC R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is a read- only bit and cannot be modified.
Page 333 Section 9 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGFA R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register •...
Page 334: Timer Counter (Tcnt)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.6 Timer Counter (TCNT) TCNT is a 16-bit readable/writable counter. The TPU has six TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in hardware standby mode. TCNT cannot be accessed in 8-bit units.
Page 335: Timer Start Register (Tstr)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.8 Timer Start Register (TSTR) TSTR starts or stops operation for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Name —...
Page 336: Timer Synchronous Register (Tsyr)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Name —...
Page 337: Operation
Section 9 16-Bit Timer Pulse Unit (TPU) Operation 9.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
Page 338: Figure 9.4 Free-Running Counter Operation
Section 9 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter.
Page 339: Figure 9.5 Periodic Counter Operation
Section 9 16-Bit Timer Pulse Unit (TPU) Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DMAC activation Figure 9.5 Periodic Counter Operation Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match.
Page 340: Figure 9.7 Example Of 0-Output/1-Output Operation
Section 9 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 9.7 shows an example of 0-output and 1-output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change.
Page 341: Figure 9.9 Example Of Setting Procedure For Input Capture Operation
Section 9 16-Bit Timer Pulse Unit (TPU) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source.
Page 342: Figure 9.10 Example Of Input Capture Operation
Section 9 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 9.10 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 343: Synchronous Operation
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base.
Page 344: Figure 9.12 Example Of Synchronous Operation
Section 9 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Figure 9.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 345: Buffer Operation
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register.
Page 346: Figure 9.14 Input Capture Buffer Operation
Section 9 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the buffer register. This operation is illustrated in figure 9.14.
Page 347: Figure 9.16 Example Of Buffer Operation (1)
Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation When TGR is an output compare register Figure 9.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 348: Figure 9.17 Example Of Buffer Operation (2)
Section 9 16-Bit Timer Pulse Unit (TPU) (b) When TGR is an input capture register Figure 9.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 349: Cascaded Operation
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.
Page 350: Figure 9.19 Example Of Cascaded Operation (1)
Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Cascaded Operation Figure 9.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
Page 351: Pwm Modes
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0-, 1-, or toggle-output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle.
Page 352: Table 9.33 Pwm Output Registers And Output Pins
Section 9 16-Bit Timer Pulse Unit (TPU) PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a cycle register compare match, the output value of each pin is the initial value set in TIOR.
Page 353: Figure 9.21 Example Of Pwm Mode Setting Procedure
Section 9 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure Figure 9.21 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 354: Figure 9.22 Example Of Pwm Mode Operation (1)
Section 9 16-Bit Timer Pulse Unit (TPU) TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 9.22 Example of PWM Mode Operation (1) Figure 9.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform.
Page 355: Figure 9.24 Example Of Pwm Mode Operation (3)
Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB changed TGRA TGRB TGRB changed TGRB changed H'0000 Time 0% duty TIOCA Output does not change when compare matches in cycle register and duty register occur simultaneously...
Page 356: Phase Counting Mode
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 357: Figure 9.25 Example Of Phase Counting Mode Setting Procedure
Section 9 16-Bit Timer Pulse Unit (TPU) Example of Phase Counting Mode Setting Procedure Figure 9.25 shows an example of the phase counting mode setting procedure. Select phase counting mode with bits MD3 to Phase counting mode MD0 in TMDR. Set the CST bit in TSTR to 1 to start the count operation.
Page 358: Figure 9.26 Example Of Phase Counting Mode 1 Operation
Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. Phase counting mode 1 Figure 9.26 shows an example of phase counting mode 1 operation, and table 9.35 summarizes the TCNT up/down-count conditions.
Page 359: Figure 9.27 Example Of Phase Counting Mode 2 Operation
Section 9 16-Bit Timer Pulse Unit (TPU) (b) Phase counting mode 2 Figure 9.27 shows an example of phase counting mode 2 operation, and table 9.36 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value...
Page 360: Figure 9.28 Example Of Phase Counting Mode 3 Operation
Section 9 16-Bit Timer Pulse Unit (TPU) Phase counting mode 3 Figure 9.28 shows an example of phase counting mode 3 operation, and table 9.37 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value...
Page 361: Figure 9.29 Example Of Phase Counting Mode 4 Operation
Section 9 16-Bit Timer Pulse Unit (TPU) (d) Phase counting mode 4 Figure 9.29 shows an example of phase counting mode 4 operation, and table 9.38 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value...
Page 362 Section 9 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example Figure 9.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed.
Page 363: Figure 9.30 Phase Counting Mode Application Example
Section 9 16-Bit Timer Pulse Unit (TPU) Channel 1 Edge TCLKA TCNT_1 detection TCLKB circuit TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture) TCNT_0 TGRA_0 (speed control cycle) TGRC_0 (position control cycle) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 9.30 Phase Counting Mode Application Example Rev.
Page 364: Interrupt Sources
Section 9 16-Bit Timer Pulse Unit (TPU) Interrupt Sources There are three kinds of TPU interrupt sources: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Page 365 Section 9 16-Bit Timer Pulse Unit (TPU) DMAC Channel Name Interrupt Source Interrupt Flag Activation TGI3A TGRA_3 input capture/compare match TGFA_3 Possible TGI3B TGRB_3 input capture/compare match TGFB_3 Not possible TGI3C TGRC_3 input capture/compare match TGFC_3 Not possible TGI3D TGRD_3 input capture/compare match TGFD_3 Not possible TCI3V...
Page 366 Section 9 16-Bit Timer Pulse Unit (TPU) DMAC Channel Name Interrupt Source Interrupt Flag Activation TGI10A TGRA_4 input capture/compare match TGFA_4 Possible TGI10B TGRB_4 input capture/compare match TGFB_4 Not possible TCI10V TCNT_4 overflow TCFV_4 Not possible TCI10U TCNT_4 underflow TCFU_4 Not possible TGI11A TGRA_5 input capture/compare match...
Page 367: Dmac Activation
Section 9 16-Bit Timer Pulse Unit (TPU) DMAC Activation The DMAC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller (DMAC). A total of six TPU input capture/compare match interrupts can be used as DMAC activation sources, one for each channel.
Page 368: Operation Timing
Section 9 16-Bit Timer Pulse Unit (TPU) Operation Timing 9.8.1 Input/Output Timing TCNT Count Timing Figure 9.31 shows TCNT count timing in internal clock operation, and figure 9.32 shows TCNT count timing in external clock operation. Pφ Falling edge Rising edge Falling edge Internal clock TCNT input...
Page 369: Figure 9.33 Output Compare Output Timing
Section 9 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
Page 370: Figure 9.35 Counter Clear Timing (Compare Match)
Section 9 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture Figure 9.35 shows the timing when counter clearing by compare match occurrence is specified, and figure 9.36 shows the timing when counter clearing by input capture occurrence is specified. Pφ...
Page 371: Figure 9.37 Buffer Operation Timing (Compare Match)
Section 9 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing Figures 9.37 and 9.38 show the timings in buffer operation. Pφ TCNT n + 1 Compare match signal TGRA, TGRB TGRC, TGRD Figure 9.37 Buffer Operation Timing (Compare Match) Pφ Input capture signal N + 1...
Page 372: Interrupt Signal Timing
Section 9 16-Bit Timer Pulse Unit (TPU) 9.8.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 9.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. Pφ...
Page 373: Figure 9.41 Tciv Interrupt Setting Timing
Section 9 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing Figure 9.41 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 9.42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing.
Page 374: Figure 9.43 Timing For Status Flag Clearing By Cpu
Section 9 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is activated, the flag is cleared automatically. Figure 9.43 shows the timing for status flag clearing by the CPU, and figure 9.44 shows the timing for status flag clearing by the DMAC.
Page 375: Usage Notes
Section 9 16-Bit Timer Pulse Unit (TPU) DMAC DMAC read cycle write cycle Pφ Address Source address Destination address Period in which the next transfer request is masked Status flag Period of flag clearing Interrupt request Period of interrupt request signal clearing signal Figure 9.45 Timing for Status Flag Clearing by DMAC Activation (2) Usage Notes...
Page 376: Caution On Cycle Setting
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: Pφ...
Page 377: Conflict Between Tcnt Write And Increment Operations
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.5 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.48 shows the timing in this case. TCNT write cycle Pφ...
Page 378: Conflict Between Buffer Register Write And Compare Match
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.7 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data. Figure 9.50 shows the timing in this case.
Page 379: Conflict Between Tgr Write And Input Capture
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.9 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 9.52 shows the timing in this case.
Page 380: Conflict Between Overflow/Underflow And Counter Clearing
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.11 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.54 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Page 381: Multiplexing Of I/O Pins
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin.
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Page 383: Section 10 Programmable Pulse Generator (Ppg)
Section 10 Programmable Pulse Generator (PPG) Section 10 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 and 2) that can operate both simultaneously and independently.
Page 384: Input/Output Pins
Section 10 Programmable Pulse Generator (PPG) 10.2 Input/Output Pins Table 10.1 shows the PPG pin configuration. Table 10.1 Pin Configuration Pin Name Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output Group 2 pulse output PO10 Output Output...
Page 385: Register Descriptions
Section 10 Programmable Pulse Generator (PPG) 10.3 Register Descriptions The PPG has the following registers. • Next data enable register H (NDERH) • Next data enable register L (NDERL) • Output data register H (PODRH) • Output data register L (PODRL) •...
Page 386 Section 10 Programmable Pulse Generator (PPG) • NDERH Initial Bit Name Value Description NDER15 Next Data Enable 15 to 8 NDER14 When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected NDER13 output trigger.
Page 387: Output Data Registers H, L (Podrh, Podrl)
Section 10 Programmable Pulse Generator (PPG) 10.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. •...
Page 388: Next Data Registers H, L (Ndrh, Ndrl)
Section 10 Programmable Pulse Generator (PPG) • PODRL Initial Bit Name Value Description POD7 Output Data Register 7 to 0 POD6 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register POD5 during PPG operation.
Page 389 Section 10 Programmable Pulse Generator (PPG) • NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Initial Bit Name Value Description...
Page 390 Section 10 Programmable Pulse Generator (PPG) • NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Initial Bit Name Value Description...
Page 391: Ppg Output Control Register (Pcr)
Section 10 Programmable Pulse Generator (PPG) 10.3.4 PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 10.3.5, PPG Output Mode Register (PMR). G3CMS1 G3CMS0 G2CMS1 G2CMS0 —...
Page 392: Ppg Output Mode Register (Pmr)
Section 10 Programmable Pulse Generator (PPG) 10.3.5 PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger.
Page 393 Section 10 Programmable Pulse Generator (PPG) Initial Bit Name Value Description G3NOV Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) G2NOV...
Page 394: Operation
Section 10 Programmable Pulse Generator (PPG) 10.4 Operation Figure 10.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting.
Page 395: Sample Setup Procedure For Normal Pulse Output
Section 10 Programmable Pulse Generator (PPG) 10.4.2 Sample Setup Procedure for Normal Pulse Output Figure 10.4 shows a sample procedure for setting up normal pulse output. Set TIOR to make TGRA an output Normal PPG output compare register (with output disabled). Set the PPG output trigger cycle.
Page 396: Example Of Normal Pulse Output (Example Of 5-Phase Pulse Output)
Section 10 Programmable Pulse Generator (PPG) 10.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output) Figure 10.5 shows an example in which pulse output is used for cyclic 5-phase pulse output. Compare match TCNT value TCNT TGRA H'0000 Time NDRH PODRH...
Page 397: Non-Overlapping Pulse Output
Section 10 Programmable Pulse Generator (PPG) 10.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: • At compare match A, the NDR bits are always transferred to PODR. • At compare match B, the NDR bits are transferred only if their value is 0. The NDR bits are not transferred if their value is 1.
Page 398: Figure 10.7 Non-Overlapping Operation And Ndr Write Timing
Section 10 Programmable Pulse Generator (PPG) Figure 10.7 shows the timing of this operation. Compare match A Compare match B Write to NDR Write to NDR PODR 0 output 0/1 output 0 output 0/1 output Write to NDR Write to NDR here here Do not write...
Page 399: Sample Setup Procedure For Non-Overlapping Pulse Output
Section 10 Programmable Pulse Generator (PPG) 10.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 10.8 shows a sample procedure for setting up non-overlapping pulse output. Set TIOR to make TGRA and TGRB Non-overlapping output compare registers (with output pulse output disabled).
Page 400: Example Of Non-Overlapping Pulse Output (Example Of 4-Phase Complementary Non-Overlapping Pulse Output)
Section 10 Programmable Pulse Generator (PPG) 10.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output) Figure 10.9 shows an example in which pulse output is used for 4-phase complementary non- overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000...
Page 401 Section 10 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the cycle in TGRB and the non-overlapping margin in TGRA, and set the counter to be cleared by compare match B.
Page 402: Inverted Pulse Output
Section 10 Programmable Pulse Generator (PPG) 10.4.7 Inverted Pulse Output If the G3INV and G2INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 10.10 shows the outputs when the G3INV and G2INV bits are cleared to 0, in addition to the settings of figure 10.9.
Page 403: Pulse Output Triggered By Input Capture
Section 10 Programmable Pulse Generator (PPG) 10.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal.
Page 404 Section 10 Programmable Pulse Generator (PPG) Rev. 3.00 Mar. 14, 2006 Page 366 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 405: Section 11 Watchdog Timer (Wdt)
Section 11 Watchdog Timer (WDT) Section 11 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an internal reset signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer.
Page 406: Register Descriptions
Section 11 Watchdog Timer (WDT) 11.2 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, see section 11.5.1, Notes on Register Access. •...
Page 407: Timer Control/Status Register (Tcsr)
Section 11 Watchdog Timer (WDT) 11.2.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. Bit Name WT/IT — — CKS2 CKS1 CKS0 Initial Value R/(W)* Note: * Only 0 can be written to this bit, to clear the flag. Initial Bit Name Value...
Page 408: Reset Control/Status Register (Rstcsr)
Section 11 Watchdog Timer (WDT) Initial Bit Name Value Description Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00.  4, 3 All 1 Reserved These are read-only bits and cannot be modified.
Page 409 Section 11 Watchdog Timer (WDT) Initial Bit Name Value Description WOVF R/(W)* Watchdog Timer Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] •...
Page 410: Operation
Section 11 Watchdog Timer (WDT) 11.3 Operation 11.3.1 Watchdog Timer Mode To use the WDT in watchdog timer mode, set both the WT/IT and TME bits in TCSR to 1. When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. When the watchdog timer mode is selected and the RSTE bit in RSTCSR is set to 1, if TCNT overflows without being rewritten because of a system crash or other error, this LSI is initialized internally.
Page 411: Interval Timer Mode
Section 11 Watchdog Timer (WDT) 11.3.2 Interval Timer Mode To use the WDT as an interval timer, set the WT/IT bit to 0 and the TME bit to 1 in TCSR. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows.
Page 412: Usage Notes
Section 11 Watchdog Timer (WDT) 11.5 Usage Notes 11.5.1 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below.
Page 413: Conflict Between Timer Counter (Tcnt) Write And Increment
Section 11 Watchdog Timer (WDT) Reading from TCNT, TCSR, and RSTCSR These registers can be read from in the same way as other registers. For reading, TCSR is assigned to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7. 11.5.2 Conflict between Timer Counter (TCNT) Write and Increment If a TCNT clock pulse is generated during the T2 state of a TCNT write cycle, the write takes...
Page 414: Transition To Watchdog Timer Mode Or Software Standby Mode
Section 11 Watchdog Timer (WDT) 11.5.5 Transition to Watchdog Timer Mode or Software Standby Mode When the WDT operates in watchdog timer mode, a transition to software standby mode is not made even when the SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1. Instead, a transition to sleep mode is made.
Page 415: Section 12 Serial Communication Interface (Sci)
Section 12 Serial Communication Interface (SCI) Section 12 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Page 416: Figure 12.1 Block Diagram Of Sci
Section 12 Serial Communication Interface (SCI) Clocked Synchronous Mode: • Data length: 8 bits • Receive error detection: Overrun errors Smart Card Interface: • An error signal can be automatically transmitted on detection of a parity error during reception • Data can be automatically re-transmitted on receiving an error signal during transmission •...
Page 417: Input/Output Pins
Section 12 Serial Communication Interface (SCI) 12.2 Input/Output Pins Table 12.1 lists the pin configuration of the SCI. Table 12.1 Pin Configuration Channel Pin Name* Function SCK3 Channel 3 clock input/output RxD3 Input Channel 3 receive data input TxD3 Output Channel 3 transmit data output SCK4 Channel 4 clock input/output...
Page 418: Register Descriptions
Section 12 Serial Communication Interface (SCI) 12.3 Register Descriptions The SCI has the following registers. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modes: Normal serial communication interface mode and smart card interface mode. The bits, therefore, are described separately for each mode in the corresponding register sections.
Page 419: Receive Shift Register (Rsr)
Section 12 Serial Communication Interface (SCI) 12.3.1 Receive Shift Register (RSR) RSR is a shift register which is used to receive serial data input from the RxD pin and converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically.
Page 420: Transmit Shift Register (Tsr)
Section 12 Serial Communication Interface (SCI) 12.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU.
Page 421 Section 12 Serial Communication Interface (SCI) Initial Bit Name Value Description Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception.
Page 422 Section 12 Serial Communication Interface (SCI) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Initial Bit Name Value Description GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended.
Page 423: Serial Control Register (Scr)
Section 12 Serial Communication Interface (SCI) Initial Bit Name Value Description CKS1 Clock Select 1,0 CKS0 These bits select the clock source for the baud rate generator. 00: Pφ clock (n = 0) 01: Pφ/4 clock (n = 1) 10: Pφ/16 clock (n = 2) 11: Pφ/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 12.3.9, Bit Rate Register (BRR).
Page 424 Section 12 Serial Communication Interface (SCI) Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Initial Bit Name Value Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled.
Page 425 Section 12 Serial Communication Interface (SCI) Initial Bit Name Value Description MPIE Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled.
Page 426 Section 12 Serial Communication Interface (SCI) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Initial Bit Name Value Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0.
Page 427: Serial Status Register (Ssr)
Section 12 Serial Communication Interface (SCI) Initial Bit Name Value Description CKE1 Clock Enable 1, 0 CKE0 These bits control the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 12.7.8, Clock Output Control. •...
Page 428 Section 12 Serial Communication Interface (SCI) Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Initial Bit Name Value Description TDRE R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 •...
Page 429 Section 12 Serial Communication Interface (SCI) Initial Bit Name Value Description ORER R/(W)* Overrun Error Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] • When the next serial reception is completed while RDRF = 1 In RDR, receive data prior to an overrun error occurrence is retained, but data received after the...
Page 430 Section 12 Serial Communication Interface (SCI) Initial Bit Name Value Description R/(W)* Parity Error Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] • When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set.
Page 431 Section 12 Serial Communication Interface (SCI) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Initial Bit Name Value Description TDRE R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 •...
Page 432 Section 12 Serial Communication Interface (SCI) Initial Bit Name Value Description ORER R/(W)* Overrun Error Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] • When the next serial reception is completed while RDRF = 1 In RDR, the receive data prior to an overrun error occurrence is retained, but data received following the...
Page 433 Section 12 Serial Communication Interface (SCI) Initial Bit Name Value Description R/(W)* Parity Error Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] • When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set.
Page 434 Section 12 Serial Communication Interface (SCI) Initial Bit Name Value Description TEND Transmit End This bit is set to 1 when no error signal is sent from the receiving side and the next transmit data is ready to be transferred to TDR. [Setting conditions] •...
Page 435: Smart Card Mode Register (Scmr)
Section 12 Serial Communication Interface (SCI) 12.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit Name — — — — SDIR SINV — SMIF Initial Value Initial Bit Name Value Description  7 to 4 All 1 Reserved These are read-only bits and cannot be modified.
Page 436: Bit Rate Register (Brr)
Section 12 Serial Communication Interface (SCI) 12.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 12.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode.
Page 437: Table 12.3 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (1)
Section 12 Serial Communication Interface (SCI) Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency Pφ (MHz) 9.8304 Rate Error Error Error Error (bit/s) 0.03 –0.26 –0.25 0.03 0.16 0.00 0.16 0.16 0.16 0.00 0.16 0.16 0.16...
Page 438: Table 12.3 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (2)
Section 12 Serial Communication Interface (SCI) Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency Pφ (MHz) 17.2032 19.6608 Bit Rate Error Error Error (bit/s) Error (%) n 0.48 –0.12 0.31 –0.25 0.00 0.16 0.00 0.16 0.00...
Page 439: Table 12.4 Maximum Bit Rate For Each Operating Frequency (Asynchronous Mode)
Section 12 Serial Communication Interface (SCI) Table 12.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) Maximum Maximum Bit Rate Bit Rate (bit/s) (bit/s) Pφ (MHz) Pφ (MHz) 250000 17.2032 537600 9.8304 307200 562500 312500 19.6608 614400 375000 625000 12.288 384000 781250...
Page 440: Table 12.6 Brr Settings For Various Bit Rates (Clocked Synchronous Mode)
Section 12 Serial Communication Interface (SCI) Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency Pφ (MHz) Bit Rate (bit/s)           2.5k 100k 250k 500k 2.5M Rev. 3.00 Mar. 14, 2006 Page 402 of 804 REJ09B0104-0300 Downloaded from Elcodis.com...
Page 441: Table 12.7 Maximum Bit Rate With External Clock Input (Clocked Synchronous Mode)
Section 12 Serial Communication Interface (SCI) Operating Frequency Pφ (MHz) Bit Rate (bit/s) 2.5k 100k 250k       500k               2.5M   ...
Page 442: Table 12.8 Brr Settings For Various Bit Rates (Smart Card Interface Mode, N = 0, S = 372)
Section 12 Serial Communication Interface (SCI) Table 12.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Operating Frequency Pφ (MHz) 7.1424 10.00 10.7136 13.00 Bit Rate (bit/s) Error (%) n Error (%) n Error (%) n Error (%) 9600...
Page 443: Operation In Asynchronous Mode
Section 12 Serial Communication Interface (SCI) 12.4 Operation in Asynchronous Mode Figure 12.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level).
Page 444: Data Transfer Format
Section 12 Serial Communication Interface (SCI) 12.4.1 Data Transfer Format Table 12.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 12.5, Multiprocessor Communication Function.
Page 445: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
Section 12 Serial Communication Interface (SCI) 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 446: Clock
Section 12 Serial Communication Interface (SCI) 12.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR.
Page 447: Sci Initialization (Asynchronous Mode)
Section 12 Serial Communication Interface (SCI) 12.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change.
Page 448: Serial Data Transmission (Asynchronous Mode)
Section 12 Serial Communication Interface (SCI) 12.4.5 Serial Data Transmission (Asynchronous Mode) Figure 12.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 449: Figure 12.7 Sample Serial Transmission Flowchart
Section 12 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a 1 is output for a frame, and transmission is enabled.
Page 450: Serial Data Reception (Asynchronous Mode)
Section 12 Serial Communication Interface (SCI) 12.4.6 Serial Data Reception (Asynchronous Mode) Figure 12.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, stores receive data in RSR, and checks the parity bit and stop bit.
Page 451: Table 12.11 Ssr Status Flags And Receive Data Handling
Section 12 Serial Communication Interface (SCI) Table 12.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Page 452: Figure 12.9 Sample Serial Reception Flowchart (1)
Section 12 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Page 453: Figure 12.9 Sample Serial Reception Flowchart (2)
Section 12 Serial Communication Interface (SCI) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 PER = 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End>...
Page 454: Multiprocessor Communication Function
Section 12 Serial Communication Interface (SCI) 12.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
Page 455: Figure 12.10 Example Of Communication Using Multiprocessor Format (Transmission Of Data H'aa To Receiving Station A)
Section 12 Serial Communication Interface (SCI) Transmitting station Communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle =...
Page 456: Multiprocessor Serial Data Transmission
Section 12 Serial Communication Interface (SCI) 12.5.1 Multiprocessor Serial Data Transmission Figure 12.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission.
Page 457: Multiprocessor Serial Data Reception
Section 12 Serial Communication Interface (SCI) 12.5.2 Multiprocessor Serial Data Reception Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 458: Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)
Section 12 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] ID reception cycle: Set the MPIE bit in SCR to 1. Set MPIE bit in SCR to 1 [3] SCI state check, ID reception and comparison: Read ORER and FER flags in SSR...
Page 459: Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)
Section 12 Serial Communication Interface (SCI) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.
Page 460: Operation In Clocked Synchronous Mode
Section 12 Serial Communication Interface (SCI) 12.6 Operation in Clocked Synchronous Mode Figure 12.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next.
Page 461: Sci Initialization (Clocked Synchronous Mode)
Section 12 Serial Communication Interface (SCI) 12.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change.
Page 462: Serial Data Transmission (Clocked Synchronous Mode)
Section 12 Serial Communication Interface (SCI) 12.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 12.16 shows an example of the operation for transmission in clocked synchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 463: Figure 12.16 Example Of Operation For Transmission In Clocked Synchronous Mode
Section 12 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to TDR TXI interrupt TEI interrupt request request generated and TDRE flag cleared request generated generated...
Page 464: Serial Data Reception (Clocked Synchronous Mode)
Section 12 Serial Communication Interface (SCI) 12.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 12.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR.
Page 465: Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode)
Section 12 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing: Read ORER flag in SSR If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error ORER = 1...
Page 466: Figure 12.20 Sample Flowchart Of Simultaneous Serial Transmission And Reception
Section 12 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the Start transmission/reception receive data input pin, enabling simultaneous transmit and receive operations.
Page 467: Operation In Smart Card Interface Mode
Section 12 Serial Communication Interface (SCI) 12.7 Operation in Smart Card Interface Mode The SCI supports the IC card (smart card) interface, conforming to ISO/IEC 7816-3 (Identification Card) standard, as an extended serial communication interface function. Smart card interface mode can be selected using the appropriate register. 12.7.1 Sample Connection Figure 12.21 shows a sample connection between the smart card and this LSI.
Page 468: Data Format (Except In Block Transfer Mode)
Section 12 Serial Communication Interface (SCI) 12.7.2 Data Format (Except in Block Transfer Mode) Figure 12.22 shows the data transfer formats in smart card interface mode. • One frame contains 8-bit data and a parity bit in asynchronous mode. • During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame.
Page 469: Block Transfer Mode
Section 12 Serial Communication Interface (SCI) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 12.23. Therefore, data in the start character in the figure is H'3B.
Page 470: Receive Data Sampling Timing And Reception Margin
Section 12 Serial Communication Interface (SCI) 12.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. In this mode, the SCI can operate on a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings (the frequency is always 16 times the bit rate in normal asynchronous mode).
Page 471: Initialization
Section 12 Serial Communication Interface (SCI) 12.7.5 Initialization Before transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2.
Page 472: Data Transmission (Except In Block Transfer Mode)
Section 12 Serial Communication Interface (SCI) 12.7.6 Data Transmission (Except in Block Transfer Mode) Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data can be re-transmitted.
Page 473: Figure 12.26 Data Re-Transfer Operation In Sci Transmission Mode
Section 12 Serial Communication Interface (SCI) (n + 1) th nth transfer frame Retransfer frame transfer frame (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 TDRE Transfer from TDR to TSR Transfer from TDR to TSR...
Page 474: Figure 12.28 Sample Transmission Flowchart
Section 12 Serial Communication Interface (SCI) Start Initialization Start transmission ERS = 0 ? Error processing TEND = 1 ? Write data to TDR and clear TDRE flag in SSR to 0 All data transmitted? ERS = 0 ? Error processing TEND = 1 ? Clear TE bit in SCR to 0 Figure 12.28 Sample Transmission Flowchart...
Page 475: Serial Data Reception (Except In Block Transfer Mode)
Section 12 Serial Communication Interface (SCI) 12.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is similar to that in normal serial communication interface mode. Figure 12.29 shows the data re-transfer operation during reception. 1.
Page 476: Clock Output Control
Section 12 Serial Communication Interface (SCI) Start Initialization Start reception ORER = 0 and PER = 0? Error processing RDRF = 1? Read data from RDR and clear RDRF flag in SSR to 0 All data received? Clear RE bit in SCR to 0 Figure 12.30 Sample Reception Flowchart 12.7.8 Clock Output Control...
Page 477: Figure 12.32 Clock Stop And Restart Procedure
Section 12 Serial Communication Interface (SCI) At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty cycle. • At power-on To secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure.
Page 478: Interrupt Sources
Section 12 Serial Communication Interface (SCI) 12.8 Interrupt Sources 12.8.1 Interrupts in Normal Serial Communication Interface Mode Table 12.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR.
Page 479: Interrupts In Smart Card Interface Mode
Section 12 Serial Communication Interface (SCI) 12.8.2 Interrupts in Smart Card Interface Mode Table 12.13 shows the interrupt sources in smart card interface mode. A transmit end (TEI) interrupt request cannot be used in this mode. Table 12.13 SCI Interrupt Sources Name Interrupt Source Interrupt Flag...
Page 480: Usage Notes
Section 12 Serial Communication Interface (SCI) 12.9 Usage Notes 12.9.1 Module Stop Mode Setting Operation of the SCI can be disabled or enabled using the module stop control register. The initial setting is for operation of the SCI to be halted. Register access is enabled by clearing module stop mode.
Page 481: Relation Between Writing To Tdr And Tdre Flag
Section 12 Serial Communication Interface (SCI) 12.9.5 Relation between Writing to TDR and TDRE Flag The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR irrespective of the TDRE flag status.
Page 482: Sci Operations During Mode Transitions
Section 12 Serial Communication Interface (SCI) 12.9.7 SCI Operations during Mode Transitions Transmission Before making the transition to module stop mode or software standby mode, stop the transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during module stop mode or software standby mode depend on the port settings, and the pins output a high-level signal after mode cancellation.
Page 483: Figure 12.34 Sample Flowchart For Mode Transition During Transmission
Section 12 Serial Communication Interface (SCI) Figure 12.37 shows a sample flowchart for mode transition during reception. Transmission [1] Data being transmitted is lost All data transmitted? halfway. Data can be normally transmitted from the CPU by setting the TE bit to 1, reading SSR, writing to TDR, and Read TEND flag in SSR clearing the TDRE bit to 0 after...
Page 484: Figure 12.35 Port Pin States During Mode Transition (Internal Clock, Asynchronous Transmission)
Section 12 Serial Communication Interface (SCI) Transition to Software standby software standby Transmission start Transmission end mode canceled mode TE bit Port input/output output pin Port High output Start Stop Port input/output High output input/output output pin SCI TxD output Port Port TxD output...
Page 485: Figure 12.37 Sample Flowchart For Mode Transition During Reception
Section 12 Serial Communication Interface (SCI) Reception Read RDRF flag in SSR [1] Data being received will be invalid. RDRF = 1 Read receive data in RDR [2] Module stop mode is included. RE = 0 Make transition to software standby mode Cancel software standby mode Change operating mode? Initialization...
Page 486 Section 12 Serial Communication Interface (SCI) Rev. 3.00 Mar. 14, 2006 Page 448 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 487: Section 13 Controller Area Network (Hcan)
Section 13 Controller Area Network (HCAN) Section 13 Controller Area Network (HCAN) The HCAN is a module for controlling a controller area network (CAN) for real time communication in vehicular and industrial equipment systems, etc. For details on CAN specification, refer to Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH. The block diagram of the HCAN is shown in figure 13.1.
Page 488: Figure 13.1 Hcan Block Diagram
Section 13 Controller Area Network (HCAN) • Support for various modes  Hardware reset  Software reset  Normal status (error-active, error-passive)  Bus off status  HCAN configuration mode  HCAN sleep mode  HCAN halt mode • Other features ...
Page 489: Input/Output Pins
Section 13 Controller Area Network (HCAN) 13.2 Input/Output Pins Table 13.1 shows the HCAN pin configuration. For the use of these pins, the input buffer control registers (ICR) of the port and the HCAN monitor register (HCANMON) must be specified according to other HCAN settings.
Page 490: Register Descriptions
Section 13 Controller Area Network (HCAN) 13.3 Register Descriptions The HCAN has the following registers. • Master control register (MCR) • General status register (GSR) • Bit configuration register (BCR) • Mailbox configuration register (MBCR) • Transmit wait register (TXPR) •...
Page 491: Master Control Register (Mcr)
Section 13 Controller Area Network (HCAN) 13.3.1 Master Control Register (MCR) MCR controls the HCAN. Bit Name MCR7 — MCR5 — — MCR2 MCR1 MCR0 Initial Value Initial Bit Name Value Description MCR7 HCAN Sleep Mode Release When this bit is set to 1, the HCAN automatically exits HCAN sleep mode on detection of CAN bus operation.
Page 492: General Status Register (Gsr)
Section 13 Controller Area Network (HCAN) Initial Bit Name Value Description MCR0 Reset Request When this bit is set to 1, the HCAN enters reset mode. For details, refer to section 13.4.1, Hardware and Software Resets. [Setting conditions] • Writing 1 (software reset) [Clearing condition] •...
Page 493 Section 13 Controller Area Network (HCAN) Initial Bit Name Value Description GSR2 Message Transmission Status Flag Indicates whether the module is currently in the message transmission period. This bit cannot be modified. [Setting condition] • Start of message transmission (SOF) [Clearing condition] •...
Page 494: Bit Configuration Register (Bcr)
Section 13 Controller Area Network (HCAN) 13.3.3 Bit Configuration Register (BCR) BCR sets HCAN bit timing parameters and the baud rate. For details on parameters, refer to section 13.4.2, Initialization after Hardware Reset. Bit Name BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0...
Page 495 Section 13 Controller Area Network (HCAN) Initial Bit Name Value Description BCR14 Time Segment 2 (TSEG2) BCR13 Set the TSEG2 width within a range of 2 to 8 time quanta. BCR12 000: Setting prohibited 001: 2 time quanta 010: 3 time quanta 011: 4 time quanta 100: 5 time quanta 101: 6 time quanta...
Page 496: Mailbox Configuration Register (Mbcr)
Section 13 Controller Area Network (HCAN) 13.3.4 Mailbox Configuration Register (MBCR) MBCR sets the transfer direction for each mailbox. Bit Name MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 — Initial Value Bit Name MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 Initial Value Initial...
Page 497: Transmit Wait Register (Txpr)
Section 13 Controller Area Network (HCAN) 13.3.5 Transmit Wait Register (TXPR) TXPR makes transmit messages stored in mailboxes enter the transmit wait state (CAN bus arbitration wait). Bit Name TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 — Initial Value Bit Name TXPR15 TXPR14 TXPR13...
Page 498: Transmit Wait Cancel Register (Txcr)
Section 13 Controller Area Network (HCAN) 13.3.6 Transmit Wait Cancel Register (TXCR) TXCR cancels transmit wait messages in mailboxes. Bit Name TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 — Initial Value Bit Name TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 Initial Value Initial...
Page 499: Transmit Acknowledge Register (Txack)
Section 13 Controller Area Network (HCAN) 13.3.7 Transmit Acknowledge Register (TXACK) TXACK indicates the normal transmission of transmit messages in mailboxes. Bit Name TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 — Initial Value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Bit Name TXACK15 TXACK14...
Page 500: Abort Acknowledge Register (Aback)
Section 13 Controller Area Network (HCAN) 13.3.8 Abort Acknowledge Register (ABACK) ABACK indicates the normal cancellation of transmit messages in mailboxes. Bit Name ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 — Initial Value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Bit Name ABACK15 ABACK14...
Page 501: Receive Complete Register (Rxpr)
Section 13 Controller Area Network (HCAN) 13.3.9 Receive Complete Register (RXPR) RXPR indicates the normal reception of messages (data frame or remote frame) in mailboxes. For reception of a remote frame, when a bit in this register is set to 1, the corresponding remote request register (RFPR) bit is also set to 1 simultaneously.
Page 502: Remote Request Register (Rfpr)
Section 13 Controller Area Network (HCAN) 13.3.10 Remote Request Register (RFPR) RFPR indicates the normal reception of remote frames in mailboxes. When a bit in this register is set to 1, the corresponding receive complete register (RXPR) bit is also set to 1 simultaneously. Bit Name RFPR7 RFPR6...
Page 503: Interrupt Register (Irr)
Section 13 Controller Area Network (HCAN) 13.3.11 Interrupt Register (IRR) IRR is an interrupt status flag register. Bit Name IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 Initial Value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Bit Name — — — IRR12 —...
Page 504 Section 13 Controller Area Network (HCAN) Initial Bit Name Value Description IRR6 R/(W)* Bus Off Interrupt Flag Status flag indicating the bus off state caused by the transmit error counter. [Setting condition] When TEC ≥ 256 [Clearing condition] Writing 1 (When the CPU is used to clear this flag by writing 1 while the corresponding interrupt is enabled, be sure to read the flag after writing 1 to...
Page 505 Section 13 Controller Area Network (HCAN) Initial Bit Name Value Description IRR3 R/(W)* Transmit Overload Warning Interrupt Flag Status flag indicating the error warning state caused by the transmit error counter. [Setting condition] • When TEC ≥ 96 [Clearing condition] •...
Page 506 Section 13 Controller Area Network (HCAN) Initial Bit Name Value Description IRR0 R/(W)* Reset Interrupt Flag Status flag indicating that the HCAN module has been reset. This bit cannot be masked by the interrupt mask register (IMR). If this bit is not cleared to 0 after entering power-on reset or returning from software standby mode, interrupt processing will start immediately when the...
Page 507 Section 13 Controller Area Network (HCAN) Initial Bit Name Value Description   3, 2 All 0 Reserved These bits are always read as 0. The write value should always be 0. IRR9 Unread Interrupt Flag Status flag indicating that a receive message has been overwritten before being read.
Page 508: Mailbox Interrupt Mask Register (Mbimr)
Section 13 Controller Area Network (HCAN) 13.3.12 Mailbox Interrupt Mask Register (MBIMR) MBIMR enables or disables interrupt requests by individual mailboxes. Bit Name MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 Initial Value Bit Name MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8...
Page 509: Interrupt Mask Register (Imr)
Section 13 Controller Area Network (HCAN) 13.3.13 Interrupt Mask Register (IMR) IMR enables or disables interrupt requests by IRR interrupt flags. The reset interrupt flag cannot be masked. Bit Name IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 — Initial Value Bit Name —...
Page 510 Section 13 Controller Area Network (HCAN) Initial Bit Name Value Description IMR2 Remote Frame Request Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR2 (OVR0) is enabled. When set to 1, it is masked. IMR1 Receive Message Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR1 (RM1) is enabled.
Page 511: Receive Error Counter (Rec)
Section 13 Controller Area Network (HCAN) 13.3.14 Receive Error Counter (REC) REC functions as a counter indicating the number of receive message errors on the CAN bus. The count value is stipulated in the CAN protocol. Bit Name Initial Value 13.3.15 Transmit Error Counter (TEC) TEC functions as a counter indicating the number of transmit message errors on the CAN bus.
Page 512: Unread Message Status Register (Umsr)
Section 13 Controller Area Network (HCAN) 13.3.16 Unread Message Status Register (UMSR) UMSR indicates that a received message which has not been read is overwritten by a new receive message. In this case, the message which has not been read is lost. Bit Name UMSR7 UMSR6...
Page 513: Local Acceptance Filter Masks (Lafml, Lafmh)
Section 13 Controller Area Network (HCAN) 13.3.17 Local Acceptance Filter Masks (LAFML, LAFMH) LAFML and LAFMH mask the individual identifier bits of the message to be stored in mailbox 0. For details, refer to section 13.4.4, Message Reception. The relationship between the identifier bits and mask bits are shown in the following.
Page 514 Section 13 Controller Area Network (HCAN) • LAFML Initial Bit Name Value Description LAFML7 When this bit is set to 1, ID-7 of the receive message identifier is not compared. LAFML6 When this bit is set to 1, ID-6 of the receive message identifier is not compared.
Page 515 Section 13 Controller Area Network (HCAN) • LAFMH Initial Bit Name Value Description LAFMH7 When this bit is set to 1, ID-20 of the receive message identifier is not compared. LAFMH6 When this bit is set to 1, ID-19 of the receive message identifier is not compared.
Page 516: Message Control (Mc0 To Mc15)
Section 13 Controller Area Network (HCAN) 13.3.18 Message Control (MC0 to MC15) The message control register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message control registers are in RAM, their initial values after power-on are undefined.
Page 517 Section 13 Controller Area Network (HCAN) MCx[1] Bit Name — — — — DLC3 DLC2 DLC1 DLC0 Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined MCx[2] Bit Name — — — — — — — — Initial Value Undefined Undefined Undefined...
Page 518 Section 13 Controller Area Network (HCAN) Register Name Bit Name Description  MCx[1] 7 to 4 The initial value of these bits is undefined. They must be initialized by writing 0 or 1. 3 to 0 DLC3 to DLC0 R/W Data Length Code Set the data length of a data frame or the data length requested in a remote frame within the...
Page 519: Message Data (Md0 To Md15)
Section 13 Controller Area Network (HCAN) Register Name Bit Name Description MCx[6] 7 to 0 ID-28 to ID-21 Sets ID-28 to ID-21 in the identifier. MCx[7] 7 to 0 ID-7 to ID-0 Sets ID-7 to ID-0 in the identifier. MCx[8] 7 to 0 ID-15 to ID-8 Sets ID-15 to ID-8 in the identifier.
Page 520 Section 13 Controller Area Network (HCAN) MDx[1] Bit Name Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined MDx[2] Bit Name Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined MDx[3] Bit Name Initial Value Undefined Undefined Undefined Undefined Undefined Undefined...
Page 521: Hcan Monitor Register (Hcanmon)
Section 13 Controller Area Network (HCAN) 13.3.20 HCAN Monitor Register (HCANMON) HCANMON enables or disables an HCAN receive interrupt, controls transmission stop of the HTxD pin, and reflects the states of the HCAN pins. Bit Name — TxSTP HCANE — —...
Page 522: Operation
Section 13 Controller Area Network (HCAN) 13.4 Operation 13.4.1 Hardware and Software Resets The HCAN can be reset by a hardware reset or software reset. • Hardware Reset At power-on reset or a transition to software standby mode, the HCAN is initialized by automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR.
Page 523: Figure 13.6 Hardware Reset Flowchart
Section 13 Controller Area Network (HCAN) IRR0 Clearing The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. Since an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. Hardware reset : Settings by user : Processing by hardware...
Page 524: Figure 13.7 Software Reset Flowchart
Section 13 Controller Area Network (HCAN) MCR0 = 1 : Settings by user Bus idle? : Processing by hardware GSR3 = 1 (automatic) Initialization of REC and TEC only Correction BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization GSR3 = 1? MCR0 = 0...
Page 525: Figure 13.8 Detailed Description Of One Bit
Section 13 Controller Area Network (HCAN) Bit Rate and Bit Timing Settings The bit rate and bit timing settings are made in the bit configuration register (BCR). Settings should be made such that all CAN controllers connected to the CAN bus have the same baud rate and bit width.
Page 526: Table 13.3 Setting Range For Tseg1 And Tseg2 In Bcr
Section 13 Controller Area Network (HCAN) Time quanta (tq) is an integer multiple of the number of system clocks, and is determined by the baud rate prescaler (BRP) as follows. f is the frequency of the peripheral module clock (Pφ). tq = 2 ×...
Page 527 Section 13 Controller Area Network (HCAN) Mailbox Transmit/Receive Settings The HCAN has 16 mailboxes. Mailbox 0 is receive-only, while mailboxes 1 to 15 can be set for transmission or reception. The initial status of mailboxes 1 to 15 is for transmission. Mailbox transmit/receive settings are not initialized by a software reset.
Page 528: Message Transmission
Section 13 Controller Area Network (HCAN) 13.4.3 Message Transmission Messages are transmitted using mailboxes 1 to 15. The transmission procedure after initial settings is described below, and a transmission flowchart is shown in figure 13.9. Initialization (after hardware reset only) : Settings by user Clear IRR0 BCR setting...
Page 529 Section 13 Controller Area Network (HCAN) CPU interrupt source settings The CPU interrupt source is set by the interrupt mask register (IMR) and mailbox interrupt mask register (MBIMR). Transmission acknowledge and transmission abort acknowledge interrupts can be generated for individual mailboxes in the mailbox interrupt mask register (MBIMR). Arbitration field setting The arbitration field is set by the message control registers MCx[5] to MCx[8] in a transmit mailbox.
Page 530 Section 13 Controller Area Network (HCAN) Message transmission cancellation Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the bit for the corresponding mailbox (TXCR1 to TXCR15) to 1 in the transmit cancel register (TXCR).
Page 531: Figure 13.10 Transmit Message Cancellation Flowchart
Section 13 Controller Area Network (HCAN) Figure 13.10 shows a flowchart for transmit message cancellation. Message transmit wait TXPR setting : Settings by user : Processing by hardware Set TXCR bit corresponding to message to be canceled Cancellation possible? Message not sent Completion of message transmission Clear TXCR, TXPR TXACK = 1...
Page 532: Message Reception
Section 13 Controller Area Network (HCAN) 13.4.4 Message Reception The reception procedure after initial settings is described below. A reception flowchart is shown in figure 13.11. Initialization : Settings by user Clear IRR0 BCR setting : Processing by hardware MBCR setting Mailbox (RAM) initialization Interrupt settings Receive data setting...
Page 533 Section 13 Controller Area Network (HCAN) CPU interrupt source settings CPU interrupt source settings are made in the interrupt mask register (IMR) and mailbox interrupt register (MBIMR). The message to be received is also specified. Data frame and remote frame receive wait interrupt requests can be generated for individual mailboxes in the MBIMR.
Page 534 Section 13 Controller Area Network (HCAN) Message reception When a message is received, a CRC check is performed automatically. If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether the message can be received or not.
Page 535: Figure 13.12 Unread Message Overwrite Flowchart
Section 13 Controller Area Network (HCAN) Unread message overwrite If the receive message identifier matches the mailbox identifier, the receive message is stored in the mailbox regardless of whether the mailbox contains an unread message or not. If a message overwrite occurs, the corresponding bit (UMSR0 to UMSR15) in the unread message register (UMSR) is set.
Page 536: Hcan Sleep Mode
Section 13 Controller Area Network (HCAN) 13.4.5 HCAN Sleep Mode The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state in order to reduce current consumption. Figure 13.13 shows a flowchart of the HCAN sleep mode.
Page 537 Section 13 Controller Area Network (HCAN) HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle.
Page 538: Hcan Halt Mode
Section 13 Controller Area Network (HCAN) 13.4.6 HCAN Halt Mode The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 13.14 shows a flowchart of the HCAN halt mode. MCR1 = 1 Bus idle? Set MBCR...
Page 539: Interrupt Sources
Section 13 Controller Area Network (HCAN) 13.5 Interrupt Sources Table 13.4 lists the HCAN interrupt sources. These sources can be masked except the reset processing interrupt by power-on reset (IRR0). Masking is implemented using the mailbox interrupt mask register (MBIMR), interrupt mask register (IMR), and IRQ enable register (IER). For details on the interrupt vector of each interrupt source, refer to section 5, Interrupt Controller.
Page 540: Dmac Interface
Section 13 Controller Area Network (HCAN) 13.6 DMAC Interface The DMAC can be activated by the reception of a message in HCAN mailbox 0. When the DMAC activation is set and DMAC transfer ends, flags RXPR0 and RFPR0 are automatically cleared.
Page 541: Can Bus Interface
Section 13 Controller Area Network (HCAN) 13.7 CAN Bus Interface A bus transceiver IC is necessary to connect this LSI to a CAN bus. A Philips PCA82C250 transceiver IC is recommended. If any other product is used, confirm that it is compatible with the PCA82C250.
Page 542: Usage Notes
Section 13 Controller Area Network (HCAN) 13.8 Usage Notes 13.8.1 Module Stop Mode Setting HCAN operation can be disabled or enabled using the module stop control register. The HCAN operation is set to be halted initially. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes.
Page 543: Interrupts
Section 13 Controller Area Network (HCAN) 13.8.4 Interrupts When the mailbox interrupt mask register (MBIMR) is set, the interrupt registers (IRR8, 2, 1) are not set by reception completion, transmission completion, or transmission cancellation of the set mailboxes. 13.8.5 Error Counters In the case of error active and error passive, REC and TEC perform count up and down normally.
Page 544: Hcan Txcr Operation
Section 13 Controller Area Network (HCAN) 13.8.9 HCAN TXCR Operation 1. When the transmit wait cancel register (TXCR) is used to cancel a transmit wait message in a transmit wait mailbox, the corresponding bit to TXCR and the transmit wait register (TXPR) may not be cleared even if transmission is canceled.
Page 545: 13.8.10 Hcan Transmission Setting
Section 13 Controller Area Network (HCAN) 13.8.10 HCAN Transmission Setting With the following conditions satisfied, a previous message identifier (ID) may be collapsed when the next transmission is set or transmission is canceled within 50 µs after the previous transmission has been set in the bus idle state. •...
Page 546 Section 13 Controller Area Network (HCAN) Rev. 3.00 Mar. 14, 2006 Page 508 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 547: Section 14 Synchronous Serial Communication Unit (Ssu)
Section 14 Synchronous Serial Communication Unit (SSU) Section 14 Synchronous Serial Communication Unit (SSU) This LSI has three independent synchronous serial communication unit (SSU) channels. The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication.
Page 548: Figure 14.1 Block Diagram Of Ssu
Section 14 Synchronous Serial Communication Unit (SSU) Figure 14.1 shows a block diagram of the SSU. Module data bus Internal data bus SSCRH SSCRL SSTDR 0 SSRDR 0 SSMR SSTDR 1 SSRDR 1 SSER SSTDR 2 SSRDR 2 SSSR SSTDR 3 SSRDR 3 Control circuit Pφ...
Page 549: Input/Output Pins
Section 14 Synchronous Serial Communication Unit (SSU) 14.2 Input/Output Pins Table 14.1 shows the SSU pin configuration. Table 14.1 Pin Configuration Channel Abbr.* Function SSCK0 Channel 0 SSU clock input/output SSI0 Channel 0 SSU data input/output SSO0 Channel 0 SSU data input/output SCS0 Channel 0 SSU chip select input/output SSCK1...
Page 550: Register Descriptions
Section 14 Synchronous Serial Communication Unit (SSU) 14.3 Register Descriptions The SSU has the following registers. (1) Channel 0 • SS control register H_0 (SSCRH_0) • SS control register L_0 (SSCRL_0) • SS mode register_0 (SSMR_0) • SS enable register_0 (SSER_0) •...
Page 551 Section 14 Synchronous Serial Communication Unit (SSU) (2) Channel 1 • SS control register H_1 (SSCRH_1) • SS control register L_1 (SSCRL_1) • SS mode register_1 (SSMR_1) • SS enable register_1 (SSER_1) • SS status register_1 (SSSR_1) • SS control register 2_1 (SSCR2_1) •...
Page 552: Ss Control Register H (Sscrh)
Section 14 Synchronous Serial Communication Unit (SSU) 14.3.1 SS Control Register H (SSCRH) SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. Bit Name BIDE — SOLP SCKS CSS1 CSS0 Initial Value Initial...
Page 553 Section 14 Synchronous Serial Communication Unit (SSU) Initial Bit Name Value Description Serial Data Output Value Select The serial data output retains its level of the last bit after completion of transmission. The output level before or after transmission can be specified by setting this bit.
Page 554: Ss Control Register L (Sscrl)
Section 14 Synchronous Serial Communication Unit (SSU) 14.3.2 SS Control Register L (SSCRL) SSCRL selects operating mode, software reset, and transmit/receive data length. Bit Name — SSUMS SRES — — — DATS1 DATS0 Initial Value Initial Bit Name Value Description ...
Page 555: Ss Mode Register (Ssmr)
Section 14 Synchronous Serial Communication Unit (SSU) 14.3.3 SS Mode Register (SSMR) SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous serial communication. Bit Name CPOS CPHS — — CKS2 CKS1 CKS0 Initial Value Initial Bit Name Value...
Page 556: Ss Enable Register (Sser)
Section 14 Synchronous Serial Communication Unit (SSU) 14.3.4 SS Enable Register (SSER) SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable. Bit Name — — TEIE CEIE Initial Value Initial Bit Name Value Description Transmit Enable When this bit is set to 1, transmission is enabled.
Page 557: Ss Status Register (Sssr)
Section 14 Synchronous Serial Communication Unit (SSU) 14.3.5 SS Status Register (SSSR) SSSR is a status flag register for interrupts. Bit Name — ORER — — TEND TDRE RDRF Initial Value Initial Bit Name Value Description   Reserved This bit is always read as 0. The write value should always be 0.
Page 558 Section 14 Synchronous Serial Communication Unit (SSU) Initial Bit Name Value Description TEND Transmit End [Setting condition] • When the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is cleared to 0 and the TDRE bit is set to 1 •...
Page 559: Ss Control Register 2 (Sscr2)
Section 14 Synchronous Serial Communication Unit (SSU) Initial Bit Name Value Description Conflict/Incomplete Error Indicates that a conflict error has occurred when 0 is externally input to the SCS pin with SSUMS = 0 (SSU mode) and MSS = 1 (master mode). If the SCS pin level changes to 1 with SSUMS = 0 (SSU mode) and MSS = 0 (slave mode), an incomplete error occurs because it is determined that a master device...
Page 560 Section 14 Synchronous Serial Communication Unit (SSU) Initial Bit Name Value Description SDOS Serial Data Pin Open Drain Select Selects whether the serial data output pin is used as a CMOS or an NMOS open drain output. Pins to output serial data differ according to the register setting.
Page 561: Ss Transmit Data Registers 0 To 3 (Sstdr0 To Sstdr3)
Section 14 Synchronous Serial Communication Unit (SSU) Initial Bit Name Value Description  1, 0 All 0 Reserved These bits are always read as 0. The write value should always be 0. 14.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3) SSTDR is an 8-bit register that stores transmit data.
Page 562: Ss Receive Data Registers 0 To 3 (Ssrdr0 To Ssrdr3)
Section 14 Synchronous Serial Communication Unit (SSU) Table 14.2 Correspondence Between DATS Bit Setting and SSTDR DATS[1:0] (SSCRL[1:0]) SSTDR 11 (Setting Invalid) Valid Valid Valid Invalid Invalid Valid Valid Invalid Invalid Invalid Valid Invalid Invalid Invalid Valid Invalid 14.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) SSRDR is an 8-bit register that stores receive data.
Page 563: Ss Shift Register (Sstrsr)
Section 14 Synchronous Serial Communication Unit (SSU) Bit Name Initial Value Bit Name Initial Value Bit Name Initial Value Bit Name Initial Value Table 14.3 Correspondence Between DATS Bit Setting and SSRDR DATS[1:0] (SSCRL[1:0]) SSRDR 11 (Setting Invalid) Valid Valid Valid Invalid Invalid...
Page 564: Operation
Section 14 Synchronous Serial Communication Unit (SSU) 14.4 Operation 14.4.1 Transfer Clock A transfer clock can be selected from eight internal clocks and an external clock. When using this module, set the SCKS bit in SSCRH to 1 to select the SSCK pin as a serial clock. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin.
Page 565: Relationship Between Data Input/Output Pins And Shift Register
Section 14 Synchronous Serial Communication Unit (SSU) 14.4.3 Relationship between Data Input/Output Pins and Shift Register The connection between data input/output pins and the SS shift register (SSTRSR) depends on the combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 14.3 show the relationship.
Page 566: Communication Modes And Pin Functions
Section 14 Synchronous Serial Communication Unit (SSU) 14.4.4 Communication Modes and Pin Functions The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the communication modes and register settings. When a pin is used as an input pin, set the corresponding bit in the input buffer control register (ICR) to 1.
Page 567: Table 14.5 Communication Modes And Pin States Of Ssck Pin
Section 14 Synchronous Serial Communication Unit (SSU) Table 14.5 Communication Modes and Pin States of SSCK Pin Register Setting Pin State Communication Mode SSUMS SCKS SSCK  SSU communication mode Input  Output  Clock synchronous communication mode Input  Output [Legend] : Not used as SSU pin (can be used as I/O port)
Page 568: Ssu Mode
Section 14 Synchronous Serial Communication Unit (SSU) 14.4.5 SSU Mode In SSU mode, data communications are performed via four lines: clock line (SSCK), data input line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS). In addition, the SSU supports bidirectional mode in which a single pin functions as data input and data output lines.
Page 569 Section 14 Synchronous Serial Communication Unit (SSU) Data Transmission Figure 14.5 shows an example of transmission operation, and figure 14.6 shows a flowchart example of data transmission. When transmitting data, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock.
Page 570: Figure 14.5 Example Of Transmission Operation (Ssu Mode)
Section 14 Synchronous Serial Communication Unit (SSU) (1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0 1 frame 1 frame SSCK SSTDR0 SSTDR0 (LSB first transmission) (MSB first transmission) TDRE TEND TXI interrupt TXI interrupt TEI interrupt...
Page 571: Figure 14.6 Flowchart Example Of Data Transmission (Ssu Mode)
Section 14 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting: Specify the transmit data format. Initial setting [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming Read TDRE in SSSR that the TDRE bit is 1.
Page 572 Section 14 Synchronous Serial Communication Unit (SSU) Data Reception Figure 14.7 shows an example of reception operation, and figure 14.8 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data.
Page 573: Figure 14.7 Example Of Reception Operation (Ssu Mode)
Section 14 Synchronous Serial Communication Unit (SSU) (1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0 1 frame 1 frame SSCK SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission) RDRF RXI interrupt RXI interrupt LSI operation generated...
Page 574: Figure 14.8 Flowchart Example Of Data Reception (Ssu Mode)
Section 14 Synchronous Serial Communication Unit (SSU) Start Initial setting: Initial setting Specify the receive data format. Start reception: Dummy-read SSRDR When SSRDR is dummy-read with RE = 1, reception is started. Read SSSR [3], [6] Receive error processing: When a receive error occurs, execute the designated error RDRF = 1? processing after reading the ORER bit in SSSR.
Page 575: Figure 14.9 Flowchart Example Of Simultaneous Transmission/Reception (Ssu Mode)
Section 14 Synchronous Serial Communication Unit (SSU) Start Initial setting [1] Initial setting: Specify the transmit/receive data format. Read TDRE in SSSR [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE TDRE = 1? bit is automatically cleared to 0 and transmission/ reception is started by writing data to SSTDR.
Page 576: Scs Pin Control And Conflict Error
Section 14 Synchronous Serial Communication Unit (SSU) SCS Pin Control and Conflict Error 14.4.6 When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is cleared to 0, the SCS pin functions as an input (Hi-Z) to detect a conflict error. The detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after transfer ends.
Page 577: Clock Synchronous Communication Mode
Section 14 Synchronous Serial Communication Unit (SSU) 14.4.7 Clock Synchronous Communication Mode In clock synchronous communication mode, data communications are performed via three lines: clock line (SSCK), data input line (SSI), and data output line (SSO). Initial Settings in Clock Synchronous Communication Mode Figure 14.12 shows an example of the initial settings in clock synchronous communication mode.
Page 578: Figure 14.13 Example Of Transmission Operation (Clock Synchronous Communication Mode)
Section 14 Synchronous Serial Communication Unit (SSU) Data Transmission Figure 14.13 shows an example of transmission operation, and figure 14.14 shows a flowchart example of data transmission. When transmitting data in clock synchronous communication mode, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data.
Page 579: Figure 14.14 Flowchart Example Of Transmission Operation (Clock Synchronous Communication Mode)
Section 14 Synchronous Serial Communication Unit (SSU) Start [4][1] Initial setting: Specify the transmit data format. Initial setting [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming Read TDRE in SSSR that the TDRE bit is 1.
Page 580: Figure 14.15 Example Of Reception Operation
Section 14 Synchronous Serial Communication Unit (SSU) Data Reception Figure 14.15 shows an example of reception operation, and figure 14.16 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit in SSER to 1, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data.
Page 581: Figure 14.16 Flowchart Example Of Data Reception
Section 14 Synchronous Serial Communication Unit (SSU) Initial setting: Start Specify the receive data format. [2], [4] Receive error processing: Initial setting When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0.
Page 582: Figure 14.17 Flowchart Example Of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode)
Section 14 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting: Specify the transmit/receive data format. Initial setting [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and Read TDRE in SSSR confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission is started TDRE = 1? by writing data to SSTDR.
Page 583: Interrupt Requests
Section 14 Synchronous Serial Communication Unit (SSU) 14.5 Interrupt Requests The SSU interrupt requests are an overrun error, a conflict error, a receive data register full, transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive data register full, a transmit data register empty, and a transmit end interrupts can activate the DMAC for data transfer.
Page 584: Usage Note
Section 14 Synchronous Serial Communication Unit (SSU) 14.6 Usage Note 14.6.1 Setting of Module Stop Mode The SSU can be enabled/disabled by the module stop control register setting and is disabled by the initial value. Canceling module stop mode enables to access the SSU registers. For details, see section 19, Power-Down Modes.
Page 585: Section 15 A/D Converter
Section 15 A/D Converter Section 15 A/D Converter This LSI includes two units (unit 0 and unit 1) of successive approximation type 10-bit A/D converters that allow up to 16 analog input channels to be selected. Figures 15.1 and 15.2 are block diagrams for unit 0 and unit 1, respectively. This section describes unit 0, which has the same functions as the other unit.
Page 586 Section 15 A/D Converter Internal Module data bus data bus 10-bit D/A – Comparator Control circuit Sample-and- hold circuit ADI0 interrupt signal ADTRG0 Conversion start trigger from the TPU [Legend] ADDRD_0: A/D data register D_0 ADCR_0: A/D control register_0 ADDRE_0: A/D data register E_0 ADCSR_0: A/D control/status register_0...
Page 587: Figure 15.2 Block Diagram Of A/D Converter (Unit 1/Ad_1)
Section 15 A/D Converter Internal Module data bus data bus 10-bit D/A – AN10 Comparator Control circuit AN11 AN12 Sample-and- hold circuit AN13 AN14 AN15 ADI1 interrupt signal ADTRG1 Conversion start trigger from the TPU [Legend] ADDRD_1: A/D data register D_1 ADCR_1: A/D control register_1 ADDRE_1:...
Page 588: Input/Output Pins
Section 15 A/D Converter 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the A/D converter. Table 15.1 Pin Configuration Unit Abbr. Pin Name Symbol Function AD_0 Analog input pin 0 Input Analog inputs Analog input pin 1 Input Analog input pin 2 Input Analog input pin 3...
Page 589: Register Descriptions
Section 15 A/D Converter 15.3 Register Descriptions The A/D converter has the following registers. The registers for unit 0 (A/D_0) and unit 1 (A/D_1) have the same functions. In this descriptions, AN8 to AN15 correspond to AN0 to AN7. • Unit 0 (A/D_0) ...
Page 590: A/D Data Registers A To H (Addra To Addrh)
Section 15 A/D Converter 15.3.1 A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 15.2.
Page 591: A/D Control/Status Register (Adcsr)
Section 15 A/D Converter 15.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Name ADIE ADST — Initial Value R/(W)* Note: * Only 0 can be written to this bit, to clear the flag. Initial Bit Name Value Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
Page 592 Section 15 A/D Converter Initial Bit Name Value Description Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. • When SCANE = 0 and SCANS = X 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5...
Page 593: A/D Control Register (Adcr)
Section 15 A/D Converter 15.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion to be started by an external trigger input. Bit Name TRGS1 TRGS0 SCANE SCANS CKS1 CKS0 — — Initial Value Initial Bit Name Value Description TRGS1 Timer Trigger Select 1 and 0 TRGS0 These bits select enabling or disabling of the start of A/D conversion by a trigger signal.
Page 594: Operation
Section 15 A/D Converter 15.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion.
Page 595: Scan Mode
Section 15 A/D Converter Set* ADIE Set* Set* A/D conversion start ADST Clear* Clear* Channel 0 (AN0) Waiting for conversion operation state Waiting for Channel 1 (AN1) Waiting for conversion Waiting for conversion A/D conversion 1 A/D conversion 2 conversion operation state Channel 2 (AN2) Waiting for conversion...
Page 596: Figure 15.4 Example Of A/D Conversion (Scan Mode, Three Channels (An0 To An2) Selected)
Section 15 A/D Converter 4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state.
Page 597: Input Sampling And A/D Conversion Time
Section 15 A/D Converter 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t ) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion.
Page 598: External Trigger Input Timing
Section 15 A/D Converter Table 15.3 A/D Conversion Characteristics (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min.
Page 599: Interrupt Source
Section 15 A/D Converter 15.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 when the ADF bit in ADCSR is set to 1 after A/D conversion is completed enables ADI interrupt requests.
Page 600: Figure 15.7 A/D Conversion Accuracy Definitions
Section 15 A/D Converter Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 15.7 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error...
Page 601: Usage Notes
Section 15 A/D Converter 15.7 Usage Notes 15.7.1 Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode.
Page 602: Influences On Absolute Accuracy
Section 15 A/D Converter 15.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that digital signals on the board do not interfere with filter circuits and filter circuits do not act as antennas.
Page 603: Notes On Noise Countermeasures
Section 15 A/D Converter 15.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN15) should be connected between AVcc0, AVcc1 and AVss as shown in figure 15.10.
Page 604: A/D Input Hold Function In Software Standby Mode
Section 15 A/D Converter 5 k Ω AN0 to AN15 To A/D converter 20 pF Note: Values are reference values. Figure 15.11 Analog Input Pin Equivalent Circuit 15.7.7 A/D Input Hold Function in Software Standby Mode When this LSI enters software standby mode with A/D conversion enabled, the A/D conversion are retained, and the analog current is equal to as during A/D conversion.
Page 605: Section 16 Ram
Section 16 RAM Section 16 RAM This LSI has a 12-kbyte on-chip high-speed static RAM. The RAM is connected to the CPU by a 32-bit data bus, enabling 1-state read and 2-state write accesses by the CPU to all byte data, word data, and longword data.
Page 606 Section 16 RAM Rev. 3.00 Mar. 14, 2006 Page 568 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 607: Section 17 Flash Memory (0.18-Μm F-Ztat Version)
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Section 17 Flash Memory (0.18-µm F-ZTAT Version) The flash memory has the following features. Figure 17.1 is a block diagram of the flash memory. 17.1 Features • Size Product Classification ROM Size ROM Address H8SX/1527 R5F61527 256 kbytes...
Page 608: Figure 17.1 Block Diagram Of Flash Memory
Section 17 Flash Memory (0.18-(m F-ZTAT Version) • Programming/erasing protection Protection against programming/erasing of the flash memory can be set by hardware protection, software protection, or error protection. • Flash memory emulation function using the on-chip RAM Realtime emulation of the flash memory programming can be performed by overlaying parts of the flash memory (user MAT) area and the on-chip RAM.
Page 609: Mode Transition Diagram
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.2 Mode Transition Diagram When the mode pins are set in the reset state and reset start is performed, this LSI enters each operating mode as shown in figure 17.2. Although the flash memory can be read in user mode, it cannot be programmed or erased.
Page 610: Table 17.1 Differences Between Boot Mode, User Program Mode, User Boot Mode
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Table 17.1 Differences between Boot Mode, User Program Mode, User Boot Mode, and Programmer Mode User Program Programmer Item Boot Mode Mode User Boot Mode Mode Programming/ On-board On-board On-board Off-board erasing programming programming programming programming...
Page 611: Memory Mat Configuration
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.3 Memory MAT Configuration The memory MATs of flash memory in this LSI consists of the 256-kbyte user MAT and 10-kbyte user boot MAT. The start addresses of the user MAT and user boot MAT are allocated to the same address.
Page 612: Block Structure
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.4 Block Structure Figure 17.4 shows the block structure of the 256-kbyte user MAT. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames stand for the addresses.
Page 613: Programming/Erasing Interface
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.5 Programming/Erasing Interface Programming/erasing of the flash memory is done by downloading an on-chip programming/erasing program to the on-chip RAM and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming/erasing interface parameters.
Page 614 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Selection of On-Chip Program to be Downloaded For programming/erasing, the FLSHE bit in the system control register (SYSCR) must be set to 1 to select user program mode. This LSI has programming/erasing programs which can be downloaded to the on-chip RAM.
Page 615: Input/Output Pins
Section 17 Flash Memory (0.18-(m F-ZTAT Version) When Programming/Erasing is Executed Consecutively When processing does not end by 128-byte programming or 1-block erasure, consecutive programming/erasing can be realized by updating the start address of the programming destination and program data, or the erase block number. Since the downloaded on-chip program is left in the on-chip RAM even after programming/erasing completes, download and initialization are not required when the same processing is executed consecutively.
Page 616: Register Descriptions
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.7 Register Descriptions The flash memory has the following registers. To access these registers, the FLSHE bit in the system control register (SYSCR) must be set to 1. For details on SYSCR, see section 3.2.2, System Control Register (SYSCR).
Page 617: Programming/Erasing Interface Registers
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Table 17.3 Registers/Parameters and Target Modes Down- Initiali- Program- Register/Parameter load zation ming Erasure Read Emulation      Programming/ FCCS erasing interface      FPCS registers  ...
Page 618 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Initial Bit Name Value Description  Reserved  These are read-only bits and cannot be modified.  FLER Flash Memory Error Indicates that an error has occurred during programming or erasing the flash memory. When this bit is set to 1, the flash memory enters the error protection state.
Page 619 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Initial Bit Name Value Description (R)/W* Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS or FECS is automatically downloaded in the on-chip RAM area specified by FTDAR.
Page 620 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Flash Program Code Select Register (FPCS) FPCS selects the programming program to be downloaded. Bit Name — — — — — — — PPVS Initial Value Initial Bit Name Description Value  7 to 1 All 0 Reserved These are read-only bits and cannot be modified.
Page 621 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables to download the on-chip program and perform programming/erasing of the flash memory. Bit Name Initial Value Initial Bit Name Value Description Key Code...
Page 622 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Flash MAT Select Register (FMATS) FMATS selects the user MAT or user boot MAT. Writing to FMATS should be done when a program in the on-chip RAM is being executed. Bit Name Initial Value 0/1* 0/1* 0/1*...
Page 623 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the start address of the on-chip RAM at which to download an on-chip program. FTDAR must be set before setting the SCO bit in FCCS to 1. Bit Name TDER TDA6...
Page 624: Programming/Erasing Interface Parameters
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.7.2 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the on-chip RAM area.
Page 625 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Initialization before Programming/Erasing: The on-chip program includes the initialization program. A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction.
Page 626 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Download Pass and Fail Result Parameter (DPFR: Single Byte of Start Address in On- Chip RAM Specified by FTDAR) DPFR indicates the return value of the download result. The DPFR value is used to determine the download result.
Page 627 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Flash Pass and Fail Parameter (FPFR: General Register R0L of CPU) FPFR indicates the return values of the initialization, programming, and erasure results. The meaning of the bits in FPFR varies depending on the processing. Initialization before programming/erasing FPFR indicates the return value of the initialization result.
Page 628 Section 17 Flash Memory (0.18-(m F-ZTAT Version) (b) Programming FPFR indicates the return value of the programming result. Bit Name — — Initial Bit Name Value Description    Unused Returns 0.  Programming Mode Related Setting Error Detect Detects the error protection state and returns the result.
Page 629 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Initial Bit Name Value Description    Unused Returns 0.  Write Data Address Detect When an address not in the flash memory area is specified as the start address of the storage destination for the program data, an error occurs.
Page 630 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Erasure FPFR indicates the return value of the erasure result. Bit Name — — — Initial Bit Name Value Description    Unused Returns 0.  Erasure Mode Related Setting Error Detect Detects the error protection state and returns the result.
Page 631 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Initial Bit Name Value Description  Flash Key Register Error Detect Checks the FKEY value (H'5A) before erasure starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A) ...
Page 632 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU) FPEFEQ sets the operating frequency of the CPU. The CPU operating frequency available in this LSI ranges from 8 MHz to 40 MHz. Bit Name —...
Page 633 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Flash Multipurpose Address Area Parameter (FMPAR: General Register ER1 of CPU) FMPAR stores the start address of the programming destination on the user MAT. When an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs.
Page 634 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Flash Multipurpose Data Destination Parameter (FMPDR: General Register ER0 of CPU) FMPDR stores the start address in the area which stores the data to be programmed in the user MAT. When the storage destination for the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit in FPFR.
Page 635 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU) FEBS specifies the erase block number. Settable values for the erase block numbers range from 0 to 11 (H'00000000 to H'0000000B). A value of 0 corresponds to block EB0 and a value of 11 corresponds to block EB11.
Page 636: Ram Emulation Register (Ramer)
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.7.3 RAM Emulation Register (RAMER) RAMER specifies the user MAT area overlaid with part of the on-chip RAM (H'FFA000 to H'FFAFFF) when performing emulation of programming the user MAT. RAMER should be set in user mode or user program mode.
Page 637: On-Board Programming Mode
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.8 On-Board Programming Mode When the mode pins (MD0, MD1, and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased.
Page 638: Figure 17.7 Automatic-Bit-Rate Adjustment Operation
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Serial Interface Setting by Host The SCI_4 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data, one stop bit, and no parity. When a transition to boot mode is made, the boot program embedded in this LSI is initiated. When the boot program is initiated, this LSI measures the low period of asynchronous serial communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and adjusts the bit rate of the SCI_4 to match that of the host.
Page 639: Figure 17.8 Boot Mode State Transition Diagram
Section 17 Flash Memory (0.18-(m F-ZTAT Version) State Transition Diagram The state transition after boot mode is initiated is shown in figure 17.8. (Bit rate adjustment) H'00, ..., H'00 reception H'00 transmission (adjustment completed) Boot mode initiation Bit rate adjustment (reset by boot mode) Inquiry command reception Processing of...
Page 640 Section 17 Flash Memory (0.18-(m F-ZTAT Version) 1. After boot mode is initiated, the bit rate of the SCI_4 is adjusted with that of the host. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host.
Page 641: User Program Mode
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.8.2 User Program Mode Programming/erasing of the user MAT is executed by downloading an on-chip program. The user boot MAT cannot be programmed/erased in user program mode. The programming/erasing flow is shown in figure 17.9. Since high voltage is applied to the internal flash memory during programming/erasing, a transition to the reset state or hardware standby mode must not be made during programming/erasing.
Page 642: Figure 17.10 Ram Map When Programming/Erasing Is Executed
Section 17 Flash Memory (0.18-(m F-ZTAT Version) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that is made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM. Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the on- chip program and procedure program do not overlap.
Page 643 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Programming Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and programming are shown in figure 17.11. Start programming procedure program Select on-chip program Disable interrupts and bus to be downloaded and master operation specify download...
Page 644 Section 17 Flash Memory (0.18-(m F-ZTAT Version) The program data for one programming operation is always 128 bytes. When the program data exceeds 128 bytes, the start address of the programming destination and program data parameters are updated in 128-byte units and programming is repeated. When the program data is less than 128 bytes, invalid data is filled to prepare 128-byte program data.
Page 645 Section 17 Flash Memory (0.18-(m F-ZTAT Version)  To hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed.  Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the SCO bit to 1.
Page 646 Section 17 Flash Memory (0.18-(m F-ZTAT Version)  Interrupts can be accepted during execution of the initialization program. Make sure the program storage area and stack area in the on-chip RAM and register values are not overwritten. 8. The return value in the initialization program, the FPFR parameter is determined. 9.
Page 647 Section 17 Flash Memory (0.18-(m F-ZTAT Version) 12. Programming is executed. The entry point of the programming program is a the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute programming by using the following steps. MOV.L #DLTOP+16,ER2 ;...
Page 648 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Erasing Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and erasing are shown in figure 17.12. Start erasing procedure program Select on-chip program to be downloaded and Disable interrupts and specify download bus master operation...
Page 649 Section 17 Flash Memory (0.18-(m F-ZTAT Version) The procedure program must be executed in an area other than the user MAT to be erased. Setting the SCO bit in FCCS to 1 to request download must be executed in the on-chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM and user MAT) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data.
Page 650: Figure 17.13 Repeating Procedure Of Erasing, Programming, And Ram Emulation In User Program Mode
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Procedure of Erasing, Programming, and RAM Emulation in User Program Mode By changing the on-chip RAM start address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 17.13 shows a repeating procedure of erasing, programming, and RAM emulation.
Page 651: User Boot Mode
Section 17 Flash Memory (0.18-(m F-ZTAT Version) In figure 17.13, since RAM emulation is performed, the erasing/programming program is downloaded to avoid the 4-kbyte on-chip RAM area (H'FFA000 to H'FFAFFF). Download and initialization are performed only once at the beginning. Note the following when executing the procedure program.
Page 652 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Start programming procedure program Select on-chip program to be downloaded and specify download Set FMATS to value destination by FTDAR other than H'AA to select user MAT switchover Set FKEY to H'A5 Set FKEY to H'5A Set SCO to 1 after initializing VBR and execute download Set parameter to ER0 and...
Page 653 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Memory MAT switching is enabled by setting FMATS. However note that access to a memory MAT is not allowed until memory MAT switching is completed. During memory MAT switching, the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt vector is read is undetermined.
Page 654 Section 17 Flash Memory (0.18-(m F-ZTAT Version) User MAT Erasing in User Boot Mode Figure 17.15 shows the procedure for erasing the user MAT in user boot mode. The difference between the erasing procedures in user program mode and user boot mode is the memory MAT switching as shown in figure 17.15.
Page 655: On-Chip Program And Storable Area For Program Data
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Memory MAT switching is enabled by setting FMATS. However note that access to a memory MAT is not allowed until memory MAT switching is completed. During memory MAT switching, the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt vector is read is undetermined.
Page 656: Table 17.7 Executable Memory Mat
Section 17 Flash Memory (0.18-(m F-ZTAT Version) • Switching of the memory MATs by FMATS should be needed when programming/erasing of the user MAT is operated in user boot mode. The program which switches the memory MATs should be executed from the on-chip RAM. For details, see section 17.11, Switching between User MAT and User Boot MAT.
Page 657: Table 17.8 Usable Area For Programming In User Program Mode
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Table 17.8 Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT Embedded Program Item On-Chip RAM User MAT User MAT Storage MAT ×*   Storage area for program data Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY...
Page 658: Table 17.9 Usable Area For Erasure In User Program Mode
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Table 17.9 Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Embedded Program Item On-Chip RAM User MAT User MAT Storage MAT Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY ×...
Page 659: Table 17.10 Usable Area For Programming In User Boot Mode
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Table 17.10 Usable Area for Programming in User Boot Mode Storable/Executable Area Selected MAT User Embedded On-Chip User Boot User Boot Program Item Storage MAT ×*    Storage area for program data Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY...
Page 660: Table 17.11 Usable Area For Erasure In User Boot Mode
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Table 17.11 Usable Area for Erasure in User Boot Mode Storable/Executable Area Selected MAT User Embedded On-Chip User Boot User Boot Program Item Storage MAT Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY ×...
Page 661: Protection
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.9 Protection There are three types of protection against the flash memory programming/erasing: hardware protection, software protection, and error protection. 17.9.1 Hardware Protection Programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection.
Page 662: Software Protection
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.9.2 Software Protection The software protection protects the flash memory against programming/erasing by disabling download of the programming/erasing program, using the key code, and by the RAMER setting. Table 17.13 Software Protection Function to be Protected Programming/ Item Description...
Page 663: Figure 17.16 Transitions To Error Protection State
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Error protection is canceled by a reset. Note that the reset should be released after the reset input period of at least 100 µs has passed. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error protection state has been entered.
Page 664: Flash Memory Emulation Using Ram
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.10 Flash Memory Emulation Using RAM For realtime emulation of the data written to the flash memory using the on-chip RAM, the on- chip RAM area can be overlaid with several flash memory blocks (user MAT) using the RAM emulation register (RAMER).
Page 665: Figure 17.18 Address Map Of Overlaid Ram Area
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Figure 17.18 shows an example of overlaying flash memory block area EB0. This area can be accessed via both the on-chip RAM and flash memory area. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'FF9000 H'08000...
Page 666: Figure 17.19 Programming Tuned Data
Section 17 Flash Memory (0.18-(m F-ZTAT Version) (1) Exit RAM emulation mode. (2) Transfer user-created programming/erasing procedure program. (3) Download the on-chip programming/erasing program to the area H'00000 specified by FTDAR. FTDAR setting should avoid the tuned data area. H'01000 (4) Program after erasing, if necessary.
Page 667: Switching Between User Mat And User Boot Mat
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.11 Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because the start addresses of these MATs are allocated to the same address. Switching to the user boot MAT disables programming and erasing.
Page 668: Programmer Mode
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.12 Programmer Mode Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In programmer mode, a general-purpose PROM programmer that supports the device types shown in table 17.14 can be used to write programs to the on-chip ROM without any limitation.
Page 669: Figure 17.21 Boot Program States
Section 17 Flash Memory (0.18-(m F-ZTAT Version) These boot program states are shown in figure 17.21. Reset Bit-rate-adjustment state Response Inquiry/response wait Inquiry Operations for Operations for Transition to inquiry and selection response programming/erasing Operations for erasing user MATs and user boot MATs Programming/erasing wait...
Page 670: Figure 17.22 Bit-Rate-Adjustment Sequence
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state.
Page 671: Figure 17.23 Communication Protocol Format
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 5. Memory read response This response consists of four bytes of data. One-byte command Command or response or one-byte response n-byte Command or Data n-byte response Size Checksum Command or response Error response Error code Error response Address...
Page 672: Table 17.15 Inquiry And Selection Commands
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command.
Page 673 Section 17 Flash Memory (0.18-(m F-ZTAT Version) The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40).
Page 674 Section 17 Flash Memory (0.18-(m F-ZTAT Version) (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size...
Page 675 Section 17 Flash Memory (0.18-(m F-ZTAT Version) (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clock- mode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size...
Page 676 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios. Command H'22 • Command, H'22, (one byte): Inquiry regarding multiplication ratio Response H'32 Size Number of types Number of Multiplica- ···...
Page 677 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 • Command, H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size...
Page 678 Section 17 Flash Memory (0.18-(m F-ZTAT Version) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses. Command H'24 • Command, H'24, (one byte): Inquiry regarding user boot MAT information Response H'34 Size Number of areas...
Page 679 Section 17 Flash Memory (0.18-(m F-ZTAT Version) • Area-last address (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. • SUM (one byte): Checksum Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses.
Page 680 Section 17 Flash Memory (0.18-(m F-ZTAT Version) (k) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command. Command H'3F Size Bit rate Input frequency...
Page 681 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Error Response H'BF ERROR • Error response, H'BF, (one byte): Error response to selection of new bit rate • ERROR: (one byte): Error code H'11: Sum checking error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range.
Page 682: Figure 17.24 New Bit-Rate Selection Sequence
Section 17 Flash Memory (0.18-(m F-ZTAT Version) To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%.
Page 683 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state.
Page 684 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Command Order The order for commands in the inquiry selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command.
Page 685: Table 17.16 Programming/Erasing Commands
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Programming/Erasing State A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 17.16 lists the programming/erasing commands.
Page 686: Figure 17.25 Programming Sequence
Section 17 Flash Memory (0.18-(m F-ZTAT Version) • Programming Programming is executed by the programming selection and 128-byte programming commands. Firstly, the host should send the programming selection command and select the programming method and programming MATs. There are two programming selection commands, and selection is according to the area and method for programming.
Page 687: Figure 17.26 Erasure Sequence
Section 17 Flash Memory (0.18-(m F-ZTAT Version) • Erasure Erasure is executed by the erasure selection and block erasure commands. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased.
Page 688 Section 17 Flash Memory (0.18-(m F-ZTAT Version) User Boot MAT Programming Selection The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program. Command H'42 • Command, H'42, (one byte): User boot-program programming selection Response H'06 •...
Page 689 Section 17 Flash Memory (0.18-(m F-ZTAT Version) 128-Byte Programming The boot program will use the programming program transferred by the programming selection to program the user boot MATs or user MATs in response to 128-byte programming. Command H'50 Address Data ···...
Page 690 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Command H'50 Address • Command, H'50, (one byte): 128-byte programming • Programming Address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. • SUM (one byte): Checksum Response H'06 • Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK.
Page 691 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block number • Command, H'58, (one byte): Erasure • Size (one byte): The number of bytes that represents the erase block number This is fixed to 1.
Page 692 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Memory Read The boot program will return the data in the specified address. Command H'52 Size Area Read address Read size • Command: H'52 (1 byte): Memory read • Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) •...
Page 693 Section 17 Flash Memory (0.18-(m F-ZTAT Version) User-Boot Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user-boot program, as a four-byte value. Command H'4A • Command, H'4A, (one byte): Sum check for user-boot program Response H'5A Size...
Page 694 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Response H'06 • Response, H'06, (one byte): Response to the blank check of user boot MAT If all user MATs are blank (H'FF), the boot program will return ACK. Error Response H'CC H'52 •...
Page 695: Table 17.17 Status Code
Section 17 Flash Memory (0.18-(m F-ZTAT Version) Table 17.17 Status Code Code Description H'11 Device selection wait H'12 Clock mode selection wait H'13 Bit rate selection wait H'1F Programming/erasing state transition wait (bit rate selection is completed) H'31 Programming state for erasure H'3F Programming/erasing selection wait (erasure is completed) H'4F...
Page 696: Usage Notes
Section 17 Flash Memory (0.18-(m F-ZTAT Version) 17.14 Usage Notes 1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating.
Page 697 Section 17 Flash Memory (0.18-(m F-ZTAT Version) 12. A programming/erasing program for the flash memory used in a conventional F-ZTAT H8, H8S microcomputer which does not support download of the on-chip program by setting the SCO bit in FCCS to 1 cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of the flash memory in this F-ZTAT H8SX microcomputer.
Page 698 Section 17 Flash Memory (0.18-(m F-ZTAT Version) Rev. 3.00 Mar. 14, 2006 Page 660 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 699: Section 18 Clock Pulse Generator
Section 18 Clock Pulse Generator Section 18 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (Iφ), peripheral module clock (Pφ), and external clock (Bφ). The clock pulse generator consists of an oscillator, PLL (Phase Locked Loop) circuit, and divider. Figure 18.1 shows a block diagram of the clock pulse generator.
Page 700: Register Description
Section 18 Clock Pulse Generator 18.1 Register Description The clock pulse generator has the following register. • System clock control register (SCKCR) 18.1.1 System Clock Control Register (SCKCR) SCKCR controls Bφ clock output and frequencies of the system, peripheral module, and external clocks, and selects the Bφ...
Page 701 Section 18 Clock Pulse Generator Initial Bit Name Value Description B φ Output Select 1 POSEL1 Controls the B φ output on PA7. 0: External clock (Bφ) 1: Setting prohibited  12, 11 All 0 Reserved These bits are always read as 0. The write value should always be 0.
Page 702 Section 18 Clock Pulse Generator Initial Bit Name Value Description PCK2 Peripheral Module Clock (Pφ) Select PCK1 These bits select the frequency of the peripheral module clock. The ratio to the input clock is as follows: PCK0 000: ×8 001: ×4 010: ×2 011: ×1 1XX: Setting prohibited...
Page 703: Oscillator
Section 18 Clock Pulse Generator 18.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 18.2.1 Connecting Crystal Resonator A crystal resonator can be connected as shown in the example in figure 18.2. Select the damping resistance R according to table 18.1.
Page 704: External Clock Input
Section 18 Clock Pulse Generator Table 18.2 Crystal Resonator Characteristics Frequency (MHz) Max. (Ω) Max. (pF) 18.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 18.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF.
Page 705: Usage Notes
Section 18 Clock Pulse Generator 18.5 Usage Notes 18.5.1 Notes on Clock Pulse Generator 1. The following points should be noted since the frequency of φ (Iφ: system clock and Pφ: peripheral module clock) supplied to each module changes according to the setting of SCKCR. Select a clock division ratio that is within the operation guaranteed range of clock cycle time shown in the AC timing of electrical characteristics.
Page 706: Notes On Resonator
Section 18 Clock Pulse Generator 18.5.2 Notes on Resonator Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a reference. As the parameters for the resonator will depend on the floating capacitance of the resonator and the mounting circuit, the parameters should be determined in consultation with the resonator manufacturer.
Page 707: Notes On Input Clock Frequency
Section 18 Clock Pulse Generator This LSI VCL (41) VCC (68) VSS (39) VSS (71) VCC (22) VCC (54) VSS (20) VSS (52) Note: Numbers in parenthesis are pin numbers. 1. A 0.1-µF capacitor should be used here. 2. CB is a laminated ceramic capacitor. Figure 18.7 Connection Example of Bypass Capacitor 18.5.4 Notes on Input Clock Frequency...
Page 708 Section 18 Clock Pulse Generator Rev. 3.00 Mar. 14, 2006 Page 670 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 709: Section 19 Power-Down Modes
Section 19 Power-Down Modes Section 19 Power-Down Modes This LSI has power consumption reduction functions, such as multi-clock function, module stop function, and transition function to power-down mode. 19.1 Features • Multi-clock function The frequency division ratio is settable independently for the system clock, peripheral module clock, and external bus clock.
Page 710: Register Descriptions
Section 19 Power-Down Modes Operating State Sleep Mode All-Module-Clock-Stop Mode Software Standby Mode I/O port Functions Retained Retained Notes: "Halted (retained)" in the table means that the internal register values are retained and internal operations are suspended. 1. SCI, HCAN, and SSU enter the reset state, and other peripheral modules retain their states.
Page 711: Standby Control Register (Sbycr)
Section 19 Power-Down Modes 19.2.1 Standby Control Register (SBYCR) SBYCR controls software standby mode.   Bit Name SSBY STS4 STS3 STS2 STS1 STS0 Initial Value         Bit Name Initial Value Initial Bit Name Value Description SSBY...
Page 712 Section 19 Power-Down Modes Initial Bit Name Value Description STS4 Standby Timer Select 4 to 0 STS3 These bits select the time the MCU waits for the clock to settle when software standby mode is cleared by an STS2 external interrupt. With a crystal resonator, refer to table STS1 19.2 and make a selection according to the operating frequency so that the standby time is at least equal to the...
Page 713: Module Stop Control Registers A And B (Mstpcra And Mstpcrb)
Section 19 Power-Down Modes Initial Bit Name Value Description  All 0 Reserved 7 to 0 These bits are always read as 0. The write value should always be 0. Note: The flash memory settling time must be reserved. 19.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) MSTPCRA and MSTPCRB control module stop mode.
Page 714 Section 19 Power-Down Modes • MSTPCRA Initial Bit Name Value Module ACSE All-Module-Clock-Stop Mode Enable Enables/disables all-module-clock-stop mode for reducing current consumption by stopping the bus controller and I/O ports operations when the CPU executes the SLEEP instruction after module stop mode has been set for all the on-chip peripheral modules controlled by MSTPCR.
Page 715 Section 19 Power-Down Modes • MSTPCRB Initial Bit Name Value Module MSTPB15 1 Programmable pulse generator (PPG)* MSTPB14 Reserved MSTPB13 These bits are always read as 1. The write value should always be 1. MSTPB12 1 Serial communication interface_4 (SCI_4) MSTPB11 1 Serial communication interface_3 (SCI_3) MSTPB10...
Page 716: Module Stop Control Register C (Mstpcrc)
Section 19 Power-Down Modes 19.2.3 Module Stop Control Register C (MSTPCRC) When bits MSTPC1 and MSTPC0 are set to 1, the corresponding on-chip RAM stops. Do not set the corresponding MSTPC1 and MSTPC0 bits to 1 while accessing the on-chip RAM. Bit Name MSTPC15 MSTPC14...
Page 717: Multi-Clock Function
Section 19 Power-Down Modes 19.3 Multi-Clock Function When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, a transition is made to multi-clock mode at the end of the bus cycle. In multi-clock mode, the CPU and bus masters operate on the operating clock specified by bits ICK2 to ICK0.
Page 718: Sleep Mode
Section 19 Power-Down Modes The registers of the module for which module stop mode is selected cannot be read from or written 19.5 Sleep Mode 19.5.1 Transition to Sleep Mode When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep mode.
Page 719: Software Standby Mode
Section 19 Power-Down Modes 19.7 Software Standby Mode 19.7.1 Transition to Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop. However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral functions other than the SCI, HCAN, and SSU, and the states of the I/O ports, are retained.
Page 720: Setting Oscillation Settling Time After Clearing Software Standby Mode
Section 19 Power-Down Modes 19.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode Bits STS4 to STS0 in SBYCR should be set as described below. 1. Using a crystal resonator Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time. Table 19.2 shows the standby times for operating frequencies and settings of bits STS4 to STS0.
Page 721 Section 19 Power-Down Modes Pφ* [MHz] Standby STS4 STS3 STS2 STS1 STS0 Time Unit Reserved    µs Reserved    Reserved    Reserved    Reserved    39.4 51.2 64.0 1024 78.8 102.4 128.0 2048...
Page 722: Software Standby Mode Application Example
Section 19 Power-Down Modes 19.7.4 Software Standby Mode Application Example Figure 19.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin.
Page 723: Bφ Clock Output Control
Section 19 Power-Down Modes 19.8 Bφ Clock Output Control Output of the Bφ clock can be controlled by bits PSTOP1 and POSEL1 in SCKCR, and DDR for the corresponding PA7 pin. Clearing both bits PSTOP1 and POSEL1 to 0 enables the Bφ clock output on the PA7 pin. When bit PSTOP1 is set to 1, the Bφ...
Page 724: Usage Notes
Section 19 Power-Down Modes 19.9 Usage Notes 19.9.1 I/O Port Status In software standby mode, the I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 19.9.2 Current Consumption during Oscillation Settling Standby Period Current consumption increases during the oscillation settling standby period.
Page 725: Section 20 List Of Registers
Section 20 List of Registers Section 20 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below.
Page 726: Register Addresses (Address Order)
Section 20 List of Registers 20.1 Register Addresses (Address Order) Access Number Data Cycles of Bits Width (Read/Write) Register Name Abbr. Address Module Master control register H'FEA00 HCAN 4Pφ/4Pφ General status register H'FEA01 HCAN 4Pφ/4Pφ Bit configuration register H'FEA02 HCAN 4Pφ/4Pφ...
Page 727 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Message control 1 [1] MC1[1] H'FEA28 HCAN 4Pφ/4Pφ Message control 1 [2] MC1[2] H'FEA29 HCAN 4Pφ/4Pφ Message control 1 [3] MC1[3] H'FEA2A HCAN 4Pφ/4Pφ...
Page 728 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Message control 4 [5] MC4[5] H'FEA44 HCAN 4Pφ/4Pφ Message control 4 [6] MC4[6] H'FEA45 HCAN 4Pφ/4Pφ Message control 4 [7] MC4[7] H'FEA46 HCAN 4Pφ/4Pφ...
Page 729 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Message control 8 [1] MC8[1] H'FEA60 HCAN 4Pφ/4Pφ Message control 8 [2] MC8[2] H'FEA61 HCAN 4Pφ/4Pφ Message control 8 [3] MC8[3] H'FEA62 HCAN 4Pφ/4Pφ...
Page 730 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Message control 11 [5] MC11[5] H'FEA7C HCAN 4Pφ/4Pφ Message control 11 [6] MC11[6] H'FEA7D HCAN 4Pφ/4Pφ Message control 11 [7] MC11[7] H'FEA7E HCAN 4Pφ/4Pφ...
Page 731 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Message control 15 [1] MC15[1] H'FEA98 HCAN 4Pφ/4Pφ Message control 15 [2] MC15[2] H'FEA99 HCAN 4Pφ/4Pφ Message control 15 [3] MC15[3] H'FEA9A HCAN 4Pφ/4Pφ...
Page 732 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Message data 2 [5] MD2[5] H'FEAC4 HCAN 4Pφ/4Pφ Message data 2 [6] MD2[6] H'FEAC5 HCAN 4Pφ/4Pφ Message data 2 [7] MD2[7] H'FEAC6 HCAN 4Pφ/4Pφ...
Page 733 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Message data 6 [1] MD6[1] H'FEAE0 HCAN 4Pφ/4Pφ Message data 6 [2] MD6[2] H'FEAE1 HCAN 4Pφ/4Pφ Message data 6 [3] MD6[3] H'FEAE2 HCAN 4Pφ/4Pφ...
Page 734 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Message data 9 [5] MD9[5] H'FEAFC HCAN 4Pφ/4Pφ Message data 9 [6] MD9[6] H'FEAFD HCAN 4Pφ/4Pφ Message data 9 [7] MD9[7] H'FEAFE HCAN 4Pφ/4Pφ...
Page 735 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Message data 13 [1] MD13[1] H'FEB18 HCAN 4Pφ/4Pφ Message data 13 [2] MD13[2] H'FEB19 HCAN 4Pφ/4Pφ Message data 13 [3] MD13[3] H'FEB1A HCAN 4Pφ/4Pφ...
Page 736 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) SS control register H_0 SSCRH_0 H'FF200 SSU_0 3Pφ/3Pφ SS control register L_0 SSCRL_0 H'FF201 SSU_0 3Pφ/3Pφ SS mode register_0 SSMR_0 H'FF202 SSU_0 3Pφ/3Pφ...
Page 737 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) SS control register H_2 SSCRH_2 H'FF220 SSU_2 3Pφ/3Pφ SS control register L_2 SSCRL_2 H'FF221 SSU_2 3Pφ/3Pφ SS mode register_2 SSMR_2 H'FF222 SSU_2 3Pφ/3Pφ...
Page 738 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Timer control register_6 TCR_6 H'FFB10 TPU_6 2Pφ/2Pφ Timer mode register_6 TMDR_6 H'FFB11 TPU_6 2Pφ/2Pφ Timer I/O control register H_6 TIORH_6 H'FFB12 TPU_6 2Pφ/2Pφ...
Page 739 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Timer control register_9 TCR_9 H'FFB40 TPU_9 2Pφ/2Pφ Timer mode register_9 TMDR_9 H'FFB41 TPU_9 2Pφ/2Pφ Timer I/O control register H_9 TIORH_9 H'FFB42 TPU_9 2Pφ/2Pφ...
Page 740 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Port 1 data direction register P1DDR H'FFB80 I/O port 2Pφ/2Pφ Port 2 data direction register P2DDR H'FFB81 I/O port 2Pφ/2Pφ Port 3 data direction register P3DDR H'FFB82 I/O port...
Page 741 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Port H data direction register PHDDR H'FFBA8 I/O port 2Pφ/2Pφ Port J data direction register PJDDR H'FFBAA I/O port 2Pφ/2Pφ Port K data direction register PKDDR H'FFBAB I/O port...
Page 742 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) DMA source address DSAR_1 H'FFC20 DMAC_1 2Iφ/2Iφ register_1 DMA destination address DDAR_1 H'FFC24 DMAC_1 2Iφ/2Iφ register_1 DMA offset register_1 DOFR_1 H'FFC28 DMAC_1 2Iφ/2Iφ...
Page 743 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) DMA module request select DMRSR_0 H'FFD20 DMAC_0 2Iφ/2Iφ register_0 DMA module request select DMRSR_1 H'FFD21 DMAC_1 2Iφ/2Iφ register_1 DMA module request select DMRSR_2 H'FFD22 DMAC_2...
Page 744 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) System control register SYSCR H'FFDC2 SYSTEM 2Iφ/3Iφ System clock control register SCKCR H'FFDC4 SYSTEM 2Iφ/3Iφ Standby control register SBYCR H'FFDC6 SYSTEM 2Iφ/3Iφ Module stop control register A MSTPCRA H'FFDC8 SYSTEM...
Page 745 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Timer control register_4 TCR_4 H'FFEE0 TPU_4* 2Pφ/2Pφ Timer mode register_4 TMDR_4 H'FFEE1 TPU_4* 2Pφ/2Pφ Timer I/O control register_4 TIOR_4 H'FFEE2 TPU_4* 2Pφ/2Pφ Timer interrupt enable TIER_4 H'FFEE4...
Page 746 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Port 1 data register P1DR H'FFF50 I/O port 2Pφ/2Pφ Port 2 data register P2DR H'FFF51 I/O port 2Pφ/2Pφ Port 3 data register P3DR H'FFF52 I/O port...
Page 747 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Timer start register TSTR H'FFFBC TPU* 2Pφ/2Pφ Timer synchronous register TSYR H'FFFBD TPU* 2Pφ/2Pφ Timer control register_0 TCR_0 H'FFFC0 TPU_0* 2Pφ/2Pφ Timer mode register_0 TMDR_0 H'FFFC1 TPU_0*...
Page 748 Section 20 List of Registers Access Number Data Cycles Register Name Abbr. of Bits Address Module Width (Read/Write) Timer counter_2 TCNT_2 H'FFFE6 TPU_2* 2Pφ/2Pφ Timer general registerA_2 TGRA_2 H'FFFE8 TPU_2* 2Pφ/2Pφ Timer general registerB_2 TGRB_2 H'FFFEA TPU_2* 2Pφ/2Pφ Timer control register_3 TCR_3 H'FFFF0 TPU_3*...
Page 749: Register Bits
Section 20 List of Registers 20.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Abbreviation 31/23/15/7 30/22/14/6...
Page 750 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module HCAN UMSR UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 LAFML LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0...
Page 751 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module     MC3[1] DLC3 DLC2 DLC1 DLC0 HCAN         MC3[2]      ...
Page 752 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module  MC6[5] ID-20 ID-19 ID-18 ID-17 ID-16 HCAN MC6[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC6[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC6[8]...
Page 753 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module     MC10[1] DLC3 DLC2 DLC1 DLC0 HCAN         MC10[2]      ...
Page 754 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module  MC13[5] ID-20 ID-19 ID-18 ID-17 ID-16 HCAN MC13[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC13[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC13[8]...
Page 755 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module MD1[1] HCAN MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] MD2[1] MD2[2] MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] MD4[1] MD4[2]...
Page 756 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module MD4[5] HCAN MD4[6] MD4[7] MD4[8] MD5[1] MD5[2] MD5[3] MD5[4] MD5[5] MD5[6] MD5[7] MD5[8] MD6[1] MD6[2] MD6[3] MD6[4] MD6[5] MD6[6] MD6[7] MD6[8] MD7[1] MD7[2] MD7[3] MD7[4] MD7[5] MD7[6]...
Page 757 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module MD8[1] HCAN MD8[2] MD8[3] MD8[4] MD8[5] MD8[6] MD8[7] MD8[8] MD9[1] MD9[2] MD9[3] MD9[4] MD9[5] MD9[6] MD9[7] MD9[8] MD10[1] MD10[2] MD10[3] MD10[4] MD10[5] MD10[6] MD10[7] MD10[8] MD11[1] MD11[2]...
Page 758 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module MD11[5] HCAN MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] MD12[4] MD12[5] MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1] MD14[2] MD14[3] MD14[4] MD14[5] MD14[6]...
Page 759 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module MD15[1] HCAN MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8]     HCANMON TxSTP HCANE  SSCRH_0 BIDE SOLP SCKS CSS1 CSS0 SSU_0 ...
Page 760 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module SSTDR0_1 SSU_1 SSTDR1_1 SSTDR2_1 SSTDR3_1 SSRDR0_1 SSRDR1_1 SSRDR2_1 SSRDR3_1  SSCRH_2 BIDE SOLP SCKS CSS1 CSS0 SSU_2     SSCRL_2 SSUMS SRES DATS1 DATS0 ...
Page 761 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module ADDRD_1 A/D_1       ADDRE_1       ADDRF_1       ADDRG_1  ...
Page 762 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module  TCR_7 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_7      TMDR_7 TIOR_7 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 ...
Page 763 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module TCNT_9 TPU_9 TGRA_9 TGRB_9 TGRC_9 TGRD_9  TCR_10 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_10      TMDR_10 TIOR_10 IOB3 IOB2 IOB1 IOB0...
Page 764 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR I/O port     P2DDR P23DDR P22DDR P21DDR P20DDR P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR...
Page 765 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module     P2ODR P23ODR P22ODR P21ODR P20ODR I/O port   PFCR9 TPUMS3A TPUMS3B TPUMS2 TPUMS1 TPUMS0A TPUMS0B PFCRA TPUMS11 TPUMS10 TPUMS9A TPUMS9B TPUMS8 TPUMS7 TPUMS6A TPUMS6B ...
Page 766 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module    DACR_0 DIRS RPTIE ARS1 ARS0 DMAC_0     SAT1 SAT0 DAT1 DAT0   SARIE SARA4 SARA3 SARA2 SARA1 SARA0 ...
Page 767 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module    DACR_1 DIRS RPTIE ARS1 ARS0 DMAC_1     SAT1 SAT0 DAT1 DAT0   SARIE SARA4 SARA3 SARA2 SARA1 SARA0 ...
Page 768 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module    DACR_2 DIRS RPTIE ARS1 ARS0 DMAC_2     SAT1 SAT0 DAT1 DAT0   SARIE SARA4 SARA3 SARA2 SARA1 SARA0 ...
Page 769 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module    DACR_3 DIRS RPTIE ARS1 ARS0 DMAC_3     SAT1 SAT0 DAT1 DAT0   SARIE SARA4 SARA3 SARA2 SARA1 SARA0 ...
Page 770 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module   IPRN IPRN14 IPRN13 IPRN12 IPRN10 IPRN9 IPRN8 INTC   IPRN6 IPRN5 IPRN4 IPRN2 IPRN1 IPRN0   IPRO IPRO14 IPRO13 IPRO12 IPRO10 IPRO9 IPRO8...
Page 771 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module SCR_3* MPIE TEIE CKE1 CKE0 SCI_3 TDR_3 SSR_3* TDRE RDRF ORER TEND MPBT (ERS) RDR_3      SCMR_3 SDIR SINV SMIF SMR_4* C/A (GM) STOP...
Page 772 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module  TCR_5 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_5*      TMDR_5 TIOR_5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 ...
Page 773 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module     G3CMS1 G3CMS0 G2CMS1 G2CMS0 PPG*     G3INV G2INV G3NOV G2NOV NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 NDERL...
Page 774 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module   TSTR CST5 CST4 CST3 CST2 CST1 CST0 TPU*   TSYR SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1...
Page 775 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module  TCR_2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_2*      TMDR_2 TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 ...
Page 776: Register States In Each Operating Mode
Section 20 List of Registers 20.3 Register States in Each Operating Mode Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby  Initialized Initialized Initialized Initialized HCAN  Initialized Initialized Initialized Initialized  Initialized Initialized Initialized Initialized ...
Page 777 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby      MC1[1] HCAN      MC1[2]      MC1[3]     ...
Page 778 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby      MC4[5] HCAN      MC4[6]      MC4[7]     ...
Page 779 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby      MC8[1] HCAN      MC8[2]      MC8[3]     ...
Page 780 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby      MC11[5] HCAN      MC11[6]      MC11[7]     ...
Page 781 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby      MC15[1] HCAN      MC15[2]      MC15[3]     ...
Page 782 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby      MD2[5] HCAN      MD2[6]      MD2[7]     ...
Page 783 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby      MD6[1] HCAN      MD6[2]      MD6[3]     ...
Page 784 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby      MD9[5] HCAN      MD9[6]      MD9[7]     ...
Page 785 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby      MD13[1] HCAN      MD13[2]      MD13[3]     ...
Page 786 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby  SSCRH_0 Initialized Initialized Initialized Initialized SSU_0  SSCRL_0 Initialized Initialized Initialized Initialized  SSMR_0 Initialized Initialized Initialized Initialized  SSER_0 Initialized Initialized Initialized Initialized ...
Page 787 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby  SSCRH_2 Initialized Initialized Initialized Initialized SSU_2  SSCRL_2 Initialized Initialized Initialized Initialized  SSMR_2 Initialized Initialized Initialized Initialized  SSER_2 Initialized Initialized Initialized Initialized ...
Page 788 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby     TCR_6 Initialized TPU_6     TMDR_6 Initialized     TIORH_6 Initialized     TIORL_6 Initialized ...
Page 789 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby     TCR_9 Initialized TPU_9     TMDR_9 Initialized     TIORH_9 Initialized     TIORL_9 Initialized ...
Page 790 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby     P1DDR Initialized I/O port     P2DDR Initialized     P3DDR Initialized    ...
Page 791 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby     P2ODR Initialized I/O port     PFCR9 Initialized     PFCRA Initialized    ...
Page 792 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby     DSAR_3 Initialized DMAC_3     DDAR_3 Initialized     DOFR_3 Initialized     DTCR_3 Initialized ...
Page 793 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby     MDCR Initialized SYSTEM     SYSCR Initialized     SCKCR Initialized     SBYCR Initialized ...
Page 794 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby     TCR_4 Initialized TPU_4*     TMDR_4 Initialized     TIOR_4 Initialized     TIER_4 Initialized ...
Page 795 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby     P1DR Initialized I/O port     P2DR Initialized     P3DR Initialized    ...
Page 796 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby     TCR_0 Initialized TPU_0*     TMDR_0 Initialized     TIORH_0 Initialized     TIORL_0 Initialized ...
Page 797 Section 20 List of Registers Register All-Module- Software Hardware Abbreviation Reset Sleep Module Stop Clock-Stop Standby Standby     TCR_3 Initialized TPU_3*     TMDR_3 Initialized     TIORH_3 Initialized     TIORL_3 Initialized ...
Page 798 Section 20 List of Registers Rev. 3.00 Mar. 14, 2006 Page 760 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 799: Section 21 Electrical Characteristics
Section 21 Electrical Characteristics Section 21 Electrical Characteristics 21.1 Absolute Maximum Ratings Table 21.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (except ports 4 and 5) –0.3 to V + 0.3 Input voltage (port 4) –0.3 to AV + 0.3 Input voltage (port 5)
Page 800: Dc Characteristics
Section 21 Electrical Characteristics 21.2 DC Characteristics Table 21.2 DC Characteristics (1) Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = AV = 0 V* = –40°C to +85°C (wide-range specifications) Test Item Symbol...
Page 801: Table 21.2 Dc Characteristics (2)
Section 21 Electrical Characteristics Table 21.2 DC Characteristics (2) Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = AV = 0 V* = –40°C to +85°C (wide-range specifications) Test Item Symbol...
Page 802: Ac Characteristics
Section 21 Electrical Characteristics Table 21.3 Permissible Output Currents Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = AV = 0 V*, T = –40°C to +85°C (wide-range specifications) Item Symbol Min.
Page 803: Clock Timing
Section 21 Electrical Characteristics 21.3.1 Clock Timing Table 21.4 Clock Timing Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = AV = 0 V, Iφ = 8 to 40 MHz, Pφ = 8 to 35 MHz, = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 804: Figure 21.3 Oscillation Settling Timing After Software Standby Mode
Section 21 Electrical Characteristics Oscillator Iφ NMIEG SSBY NMI exception handling Software standby mode NMI exception (power-down mode) handling Oscillation NMIEG = 1 settling time SSBY = 1 OSC2 SLEEP instruction Figure 21.3 Oscillation Settling Timing after Software Standby Mode EXTAL DEXT OSC1...
Page 805: Control Signal Timing
Section 21 Electrical Characteristics 21.3.2 Control Signal Timing Table 21.5 Control Signal Timing Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = AV = 0 V, Iφ = 8 to 40 MHz, = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 806: Timing Of On-Chip Peripheral Modules
Section 21 Electrical Characteristics Iφ NMIS NMIH NMIW IRQW IRQi* (i = 0 to 14) IRQS IRQH IRQ* (edge input) IRQS IRQ* (level input) Note: * SSIER must be set to cancel software standby mode. Figure 21.7 Interrupt Input Timing 21.3.3 Timing of On-Chip Peripheral Modules Table 21.6 Timing of On-Chip Peripheral Modules (1)
Page 807 Section 21 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions  Pulse output delay time Figure 21.12  Input clock Asynchronous Figure 21.13 Scyc cycle  Clocked synchronous Input clock pulse width SCKW Scyc  Input clock rise time Figure 21.13 SCKr ...
Page 808: Table 21.6 Timing Of On-Chip Peripheral Modules (2)
Section 21 Electrical Characteristics Table 21.6 Timing of On-Chip Peripheral Modules (2) Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = AV = 0 V, Pφ = 8 to 20 MHz, = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 809: Figure 21.8 I/O Port Input/Output Timing
Section 21 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions  Slave access time Figure 21.19  Slave out release time Figure 21.20 Note: Although the HCAN input signals are asynchronous signals, they are received as the signals in synchronization with every other rising edge of the Pφ clock (see figure 21.16).
Page 810: Figure 21.10 Tpu Input/Output Timing
Section 21 Electrical Characteristics Pφ TOCD Output compare output* TICS Input capture input* Notes: 1. TIOCA0 to TIOCA3* , TIOCB0 to TIOCB3* , TIOCC0* , TIOCC3* TIOCD0* , TIOCD3* , TIOCA6 to TIOCA11, TIOCB6 to TIOCB11, TIOCC6, TIOCC9, TIOCD6, and TIOCD9 2.
Page 811: Figure 21.14 Sci Input/Output Timing: Clocked Synchronous Mode
Section 21 Electrical Characteristics SCK3, SCK4 TxD3, TxD4 (transmit data) RxD3, RxD4 (receive data) Figure 21.14 SCI Input/Output Timing: Clocked Synchronous Mode Pφ TRGS ADTRG0, ADTRG1 Figure 21.15 A/D Converter External Trigger Input Timing Pφ HTXD HTxD (transmit data) HRXS HRXH HRxD (receive data)
Page 812: Figure 21.17 Ssu Timing (Master, Cphs = 1)
Section 21 Electrical Characteristics SCS (output) LEAD FALL RISE SSCK (output) CPOS = 1 SSCK (output) CPOS = 0 SUcyc SSO (output) SSI (input) Figure 21.17 SSU Timing (Master, CPHS = 1) SCS (output) LEAD FALL RISE SSCK (output) CPOS = 1 SSCK (output) CPOS = 0 SUcyc...
Page 813: Figure 21.19 Ssu Timing (Slave, Cphs = 1)
Section 21 Electrical Characteristics SCS (input) LEAD FALL RISE SSCK (input) CPOS = 1 SSCK (input) CPOS = 0 SUcyc SSO (input) SSI (output) Figure 21.19 SSU Timing (Slave, CPHS = 1) SCS (input) LEAD FALL RISE SSCK (input) CPOS = 1 SSCK (input) CPOS = 0 SUcyc...
Page 814: A/D Conversion Characteristics
Section 21 Electrical Characteristics 21.4 A/D Conversion Characteristics Table 21.7 A/D Conversion Characteristics Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = AV = 0 V, Pφ = 8 to 35 MHz, = –40°C to +85°C (wide-range specifications) Item Min.
Page 815: Flash Memory Characteristics
Section 21 Electrical Characteristics 21.5 Flash Memory Characteristics Table 21.8 Flash Memory Characteristics Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = AV = 0 V, Iφ = 8 to 40 MHz, Pφ = 8 to 35 MHz, = 0°C to +85°C (wide-range specifications) Test Item...
Page 816 Section 21 Electrical Characteristics Rev. 3.00 Mar. 14, 2006 Page 778 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 817: Appendix
Appendix Appendix Port States in Each Pin State Table A.1 Port States in Each Pin State Port Name MCU Operating Mode Reset Software Standby Mode Port 1 Hi-Z Keep Port 2 Hi-Z Keep Port 3 Hi-Z Keep Port 4 Hi-Z Hi-Z Port 5 Hi-Z...
Page 818: Product Lineup
Appendix Product Lineup Product Classification Product Model Marking Package (Package Code) H8SX/1527 R5F61527 R5F61527 PRQP0100KB-A (FP-100M) H8SX/1525 R5F61525 R5F61525 Rev. 3.00 Mar. 14, 2006 Page 780 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 819: Package Dimensions
Appendix Package Dimensions For the package dimensions, data in the Renesas IC Package General Catalog has priority. Figure C.1 Package Dimensions (PRQP0100KB-A) Rev. 3.00 Mar. 14, 2006 Page 781 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 820 Appendix Rev. 3.00 Mar. 14, 2006 Page 782 of 804 REJ09B0104-0300 Downloaded from Elcodis.com electronic components distributor...
Page 821: Main Revisions And Additions In This Edition
Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Section 3 MCU Operating Modes Deleted 3.2.2 System Control Register SYSCR controls MAC saturation operation bus with (SYSCR) mode for instruction fetch, and selects enables/disables the on-chip RAM and the flash memory control registers.
Page 822 Item Page Revision (See Manual for Details) 5.8.6 Interrupt Flags of Peripheral Amended Modules To clear an interrupt request flag of a peripheral module by the CPU, the flag must be read from after being cleared within the interrupt handling routine even if the peripheral module clock is not generated by dividing the system clock.
Page 823 Item Page Revision (See Manual for Details) 7.4.3 Activation Sources Added (2) Activation by On-Chip Module The interrupt request selected as an activation source Interrupt can simultaneously generate interrupt requests to the CPU. For details, see section 5, Interrupt Controller. When the DMAC is activated with DTA = 1, the interrupt request flag is automatically cleared by a DMA transfer.
Page 824 Item Page Revision (See Manual for Details) Section 11 Watchdog Timer Added (WDT) (When the CPU is used to clear this flag by writing 0 11.2.2 Timer Control/Status while the corresponding interrupt is enabled, be sure to Register (TCSR) read the flag after writing 0 to it.) •...
Page 825 Item Page Revision (See Manual for Details) 14.3.7 SS Transmit Data Added Registers 0 to 3 (SSTDR0 to Be sure not to access invalid SSTDRs. SSTDR3) Table 14.2 Correspondence Added Between DATS Bit Setting and SSTDR 14.3.8 SS Receive Data Registers Added 0 to 3 (SSRDR0 to SSRDR3) Be sure not to access invalid SSRDRs...
Page 826 Item Page Revision (See Manual for Details) Figure 14.9 Flowchart Example of Amended Simultaneous Start Transmission/Reception (SSU Initial setting Mode) Transmission/reception started (TE = 1, RE = 1) Read TDRE in SSSR Consecutive data transmission/reception? Read TEND in SSSR TEND = 1? Error processing Clear TEND in SSSR to 0 Has the 1 bit transfer...
Page 827 Item Page Revision (See Manual for Details) Figure 14.16 Flowchart Example Deleted of Data Reception Start Initial setting RE = 1 (receprion started) Read SSSR Figure 14.17 Flowchart Example Amended of Simultaneous Start Transmission/Reception Initial setting Transmission/reception started (TE = 1, RE = 1) Read TDRE in SSSR Consecutive data transmission/reception?
Page 828 Item Page Revision (See Manual for Details) Section 15 A/D Converter Added 15.1 Features Figure 15.2 Block Diagram of A/D Converter (Unit 1/AD_1) 10-bit D/A Control circuit AN14 AN15 ADI1 interrupt signal ADTRG1 Conversion start trigger from the TPU 15.3.2 A/D Control/Status Added Register (ADCSR) (When the CPU is used to clear this flag by writing 0...
Page 829 Item Page Revision (See Manual for Details) 17.7.2 Programming/Erasing Amended Interface Parameters Parameter Download Table 17.4 Parameters and Target DPFR Modes  FPFR  FPEFEQ  FMPAR  FMPDR  FEBS 17.7.2 Programming/Erasing Amended Interface Parameters Checks the FKEY value (H'5A) before erasure starts, (b) Programming and returns the result.
Page 830: Figure 17.11 Programming Procedure In User Program Mode
Item Page Revision (See Manual for Details) 17.8.2 User Program Mode Amended (2) Programming Procedure in User Program Mode Figure 17.11 Programming Disable interrupts and bus master operation Procedure in User Program Mode other than CPU Set FKEY to H'5A Set parameters to ER1 and ER0 (FMPAR and FMPDR)
Page 831: Figure 17.12 Erasing Procedure In User Program Mode
Item Page Revision (See Manual for Details) (3) Erasing Procedure in User Amended Program Mode Figure 17.12 Erasing Procedure in User Program Mode Disable interrupts and bus master operation other than CPU Set FKEY to H'5A Set FEBS parameter Erasing JSR FTDAR setting + 16 FPFR = 0? Clear FKEY and erasing...
Page 832: Figure 17.14 Procedure For Programming User Mat In User Boot Mode
Item Page Revision (See Manual for Details) 17.8.3 User Boot Mode Amended Start programming Figure 17.14 Procedure for procedure program Programming User MAT in User Select on-chip program to be downloaded and specify download Boot Mode Set FMATS to value destination by FTDAR other than H'AA to select user MAT...
Page 833 Item Page Revision (See Manual for Details) 17.13 Standard Serial Deleted Communication Interface 3. Operating frequency error Specifications for Boot Mode (4) Receive Data Check (8) Programming/Erasing State Amended Command Command Name Description H'4C User boot MAT blank check Checks the blank data of the user boot MAT H'4D User MAT blank check Checks the blank data of the user MAT...
Page 834 Item Page Revision (See Manual for Details) 18.5 Usage Notes Deleted 18.5.1 Notes on Clock Pulse 5. When Iφ > Pφ is specified by SCKCR, signals from Generator the peripheral modules must be synchronized with the system clock. When CPU instructions are used to clear the interrupt source flag of a peripheral module, the flag must be read after being cleared to Section 19 Power-Down Modes...
Page 835 Item Page Revision (See Manual for Details) Section 20 List of Registers Amended 20.1 Register Addresses Number (Address Order) Register Name Abbr. of Bits Standby control register SBYCR 20.2 Register Bits Amended Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 ...
Page 836: Figure 21.7 Interrupt Input Timing
Item Page Revision (See Manual for Details) 21.2 DC Characteristics Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = 4.5 V to 5.5 V, V = AV = 0 V* = –20°C to Table 21.2 DC Characteristics (1) +75°C (regular specifications), T = –40°C to +85°C...
Page 837: Index
Index Numerics 0-output/1-output ........302 CAN bus interface........503 11 consecutive recessive bits ....484 Clock............408 16-bit timer pulse unit (TPU) ....251 Clock pulse generator ......661 Clock synchronous communication mode ............539 Clocked synchronous mode ....422 Communications protocol .......
Page 838 Exception handling by illegal instruction ..........84 I/O ports ..........205 Exception handling vector table ....74 ID code............ 416 Exception-handling state ......64 Illegal instruction ........83 Extended repeat area....... 156 Input buffer control register ....213 Extended repeat area function ....170 Input capture function ......
Page 839 Module stop mode ........679 Processing states ........64 Multi-clock function ....... 128, 679 Product lineup ......... 780 Multiprocessor bit........416 Program execution state ......64 Multiprocessor communication Program stop state........64 function........... 416 Programmable pulse generator (PPG)..345 Programmer mode........630 Programming/erasing interface ....
Page 840 DMRSR .......157, 705, 731, 754 MSTPCRC....678, 706, 732, 755 DOFR ......139, 703, 727, 753 NDERH....... 347, 708, 735, 757 DPFR ..........588 NDERL ....... 347, 708, 735, 757 DR .......212, 708, 734, 757 NDRH ......350, 708, 735, 757 DSAR ......137, 703, 727, 753 NDRL ......
Page 841 SYSCR ......69, 706, 732, 755 Standard serial communication TCNT......296, 368, 708, 709, interface specifications for boot mode ..630 ........735, 736, 757, 758 Start bit............ 405 TCR ......265, 709, 736, 758 State transitions......... 65 TCSR ......369, 708, 735, 757 Stop bit............
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This manual is also suitable for:

H8sx/1500 series H8sx/1525 H8sx series R5f61525 H8sx/1527 R5f61527

Renesas H8SX/1520 Series Hardware Manual

Table of Contents

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller (BSC)

Section 7 DMA Controller (DMAC)

Section 8 I/O Ports

Section 9 16-Bit Timer Pulse Unit (TPU)

Section 10 Programmable Pulse Generator (PPG)

Section 11 Watchdog Timer (WDT)

Section 12 Serial Communication Interface (SCI)

Section 13 Controller Area Network (HCAN)

Section 14 Synchronous Serial Communication Unit (SSU)

Section 15 A/D Converter

Section 16 RAM

Section 17 Flash Memory (0.18-ΜM F-ZTAT Version)

Section 18 Clock Pulse Generator

Section 19 Power-Down Modes

Section 20 List of Registers

Section 21 Electrical Characteristics

Appendix

Main Revisions and Additions in this Edition

Index

Quick Links

Chapters

Related Manuals for Renesas H8SX/1520 Series

Summary of Contents for Renesas H8SX/1520 Series