Advertisement
Section 11 8-Bit Timer (TMR)
11.6
Usage Notes
11.6.1
Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T
11.7, the counter clear takes priority and the write is not performed.
φ
Address
Internal write signal
Counter clear signal
TCNT
Figure 11.7 Conflict between TCNT Write and Counter Clear
Rev. 1.00 Mar. 12, 2008 Page 408 of 1178
REJ09B0403-0100
state of a TCNT write cycle as shown in figure
2
TCNT write cycle by CPU
T 1
T 2
TCNT address
N
H'00
Advertisement
