Renesas H8S Family Hardware Manual page 600

Section 17 Synchronous Serial Communication Unit (SSU)

Figure 17.1 shows a block diagram of the SSU.

SSTDR0 to SSTDR3:

SSRDR0 to SSRDR3:

Rev. 1.00 Mar. 12, 2008 Page 552 of 1178

REJ09B0403-0100

Module data bus

SS control register H

SS control register L

SS control register 2

SS mode register

SS enable register

SS status register

SS transmit data registers 0 to 3

SS receive data registers 0 to 3

SS shift register

Figure 17.1 Block Diagram of SSU

Control circuit

SSCK (External clock)

Internal data bus