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Section 6 Bus Controller (BSC)
6.7
Idle Cycle
When this LSI accesses the external address space, it can insert a 1-state idle cycle (T
) between
I
bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM with a long output floating time, and
high-speed memory and I/O interfaces.
If an external write occurs after an external read while the ICIS bit is set to 1 in BCR, an idle cycle
is inserted at the start of the write cycle.
Figure 6.32 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle
for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.32 (a),
with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and
the CPU write data. In figure 6.32 (b), an idle cycle is inserted, thus preventing data collision.
Bus cycle A
Bus cycle B
Bus cycle A
Bus cycle B
T
T
T
T
T
T
T
T
T
T
T
1
2
3
1
2
1
2
3
I
1
2
φ
φ
Address bus
Address bus
RD
RD
WR
WR
Data bus
Data bus
Data collision
Long output floating time
(a) No idle cycle insertion
(b) Idle cycle insertion
Figure 6.32 Examples of Idle Cycle Operation
Rev. 1.00 Mar. 12, 2008 Page 154 of 1178
REJ09B0403-0100
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