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17.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 562
17.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 563
17.3.9 SS Shift Register (SSTRSR)................................................................................. 563
17.4 Operation ........................................................................................................................... 564
17.4.1 Transfer Clock ...................................................................................................... 564
17.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 564
17.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 565
17.4.4 Communication Modes and Pin Functions ........................................................... 566
17.4.5 SSU Mode............................................................................................................. 568
17.4.6 SCS Pin Control and Conflict Error...................................................................... 576
17.4.7 Clock Synchronous Communication Mode .......................................................... 577
17.5 Interrupt Requests .............................................................................................................. 583
17.6 Usage Note......................................................................................................................... 583
17.6.1 Setting of Module Stop Mode............................................................................... 583
2
Section 18 I
C Bus Interface (IIC) .....................................................................585
18.1 Features.............................................................................................................................. 585
18.2 Input/Output Pins ............................................................................................................... 588
18.3 Register Descriptions ......................................................................................................... 589
2
18.3.1 I
C Bus Data Register (ICDR) .............................................................................. 589
18.3.2 Slave Address Register (SAR).............................................................................. 590
18.3.3 Second Slave Address Register (SARX) .............................................................. 591
2
18.3.4 I
C Bus Mode Register (ICMR)............................................................................ 593
2
18.3.5 I
C Bus Transfer Rate Select Register (IICX3)..................................................... 595
2
18.3.6 I
C Bus Control Register (ICCR).......................................................................... 598
2
18.3.7 I
C Bus Status Register (ICSR)............................................................................. 607
2
18.3.8 I
C Bus Extended Control Register (ICXR).......................................................... 611
2
18.3.9 I
C SMBus Control Register (ICSMBCR)............................................................ 615
18.4 Operation ........................................................................................................................... 617
2
18.4.1 I
C Bus Data Format ............................................................................................. 617
18.4.2 Initialization .......................................................................................................... 619
18.4.3 Master Transmit Operation ................................................................................... 619
18.4.4 Master Receive Operation..................................................................................... 623
18.4.5 Slave Receive Operation....................................................................................... 632
18.4.6 Slave Transmit Operation ..................................................................................... 640
18.4.7 IRIC Setting Timing and SCL Control ................................................................. 643
18.4.8 Operation Using the DTC ..................................................................................... 646
18.4.9 Noise Canceler...................................................................................................... 648
18.4.10 Initialization of Internal State ............................................................................... 648
18.5 Interrupt Source ................................................................................................................. 650
Rev. 1.00 Mar. 12, 2008 Page xix of xIviii
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