Renesas H8S Family Hardware Manual page 195

Address
T T
1
φ
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
Figure 6.26 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access)
Address
T T
1
φ
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
Figure 6.27 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access)
Read Cycle
Data
T T T T
AW 2 3 4 DSW
Address
Address
Read Cycle
Data
T T T T
AW 2 3 4 DSW
Address
Address
Section 6 Bus Controller (BSC)
Write Cycle
Address
T T T T T
5 1 AW 2 3
Address
Data
Address
Write Cycle
Address
T T T T T
5 1 AW 2 3
Data Address
Data
Address
Rev. 1.00 Mar. 12, 2008 Page 147 of 1178
Data
T T T
4 DSW 5
Data
Data
T T T
4 DSW 5
Data
Data
REJ09B0403-0100