ST STM32L4+ Series Reference Manual page 1168

Public key accelerator (PKA) applied to STM32L4P5xx and STM32L4Q5xx only
pka_hclk
36.3.2 PKA internal signals
Table 240
bonding pads.
Signal name
pka_hclk
36.3.3 PKA reset and clocks
PKA is clocked on the AHB bus clock. The RAM receives this clock directly, the core is
clocked at half the frequency.
When the PKA peripheral reset signal is released PKA RAM is cleared automatically, taking
894 clock cycles. During this time the setting of EN bit in PKA_CR is ignored.
36.3.4 PKA public key acceleration
Overview
Public key accelerator (PKA) is used to accelerate Rivest, Shamir and Adleman (RSA),
Diffie-Hellman (DH) as well as ECC over prime field operations. Supported operand sizes is
up to 3136 bits for RSA and DH, and up to 640 bits for ECC.
A memory of 3576 bytes (894 words of 32 bits) called PKA RAM is used for providing initial
data to the PKA, and for holding the results after computation is completed. Access is done
though the PKA AHB interface.
PKA operating modes
The list of operations the PKA can perform is detailed in
respectively, for integer arithmetic functions and prime field (Fp) elliptic curve functions.
1168/2301
Figure 282. PKA block diagram
AHB
interface
IRQ
pka_it
interface
lists internal signals available at the IP level, not necessarily available on product
Table 240. Internal input/output signals
Signal type
Digital input
pka_it Digital output
Banked registers (main)
PKA_CR
control
PKA_SR
status
PKA_CLRFR
clear
Control
PKA core
logic
AHB bus clock
Public key accelerator IP global interrupt request
RM0432 Rev 6
PKA32
894x32-bit
PKA RAM
32-bit
Description
Table 241 and Table 242,
RM0432
MS45419V1