Table of Contents
Advertisement
M
1
6
C
2 /
9
G
o r
u
p
16.13 Address Data Communication
This section describes data transmit control when a master transferes data or a slave receives data in 7-bit
address format. Figure 16.20 (1) shows a master transmit format.
(1) A master transmit device transmits data to a receive device
S
(2) A master receive device receives data from a transmit device
S
S: START condition
A: ACK bit
Figure 16.20 Address data communication format
16.13.1 Example of Master Transmit
For example, a master transmits data as shown below when following conditions are met: standard clock
mode, SCL clock frequency of 100kHz and ACK clock added.
1) Set s slave address to the 7 high-order bits in the S0D0 register
2) Set 85
to the S20 register, 000
16
registe to generate an ACK clock and set SCL clock frequency t 100 kHz (f
3) Set 00
to the S10 register to reset transmit/receive
16
4) Set 08
to the S1D0 register to enable data communication
16
5) Confirm whether the bus is free by BB flag setting in the S10 register
6) Set E0
to the S10 register to enter START condition standby mode
16
7) Set the destination address in 7 high-order bits and 0 to a least significant bit in the S00 register to
generate START condition. At this time, the first byte consisting of SCL and ACK clock are auto-
matically generated
8) Set a transmit data to the S00 register. At this time, SCL and an ACK clock are automatically
generated
9) When transmitting more than 1-byte control data, repeat the above step 8).
10) Set C0
in the S10 register to enter STOP condition standby mode if ACK is not returned from the
16
slave receiver or if the transmit is completed
11) Write dummy data to the S00 regiser to generate STOP condition
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
R/W
S l a v e a d d r e s s
7 bits
0
R/W
S l a v e a d d r e s s
7 bits
1
P: STOP condition
R/W: Read/Write bit
to bits ICK4 to ICK2 in the S4D0 register and 00
2
page 282
f o
4
5
8
16. MULTI-MASTER I
A
A
D a t a
1 - 8 bits
A
A
D a t a
1 - 8 bits
2
C bus INTERFACE
A/A
P
D a t a
1 - 8 bits
A
P
D a t a
1 - 8 bits
16
=8MHz, f
1
to the S3D0
=f1)
IIC
Advertisement
Table of Contents
