Changing Value Of Cks2 To Cks0; Switching Between Watchdog Timer Mode And Interval Timer Mode; Internal Reset In Watchdog Timer Mode; Figure 13.5 Contention Between Tcnt Write And Increment - Renesas H8S/2368 Series Hardware Manual

φ
Address
Internal write signal
TCNT input clock
TCNT

Figure 13.5 Contention between TCNT Write and Increment

13.6.3

Changing Value of CKS2 to CKS0

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
13.6.4

Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors
could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME
bit to 0) before switching the mode.
13.6.5

Internal Reset in Watchdog Timer Mode

This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer mode operation, but TCNT and TCSR of the WDT are reset.
TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that
a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,
read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.
Rev. 2.00, 05/03, page 504 of 820
TCNT write cycle
T 1 T 2 Next cycle
N
Counter write data
M