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M16C/64C Group
11.4
Notes on Bus
11.4.1
Reading Data Flash
When 2.7 V ≤ VCC1 ≤ 3.0 V and f(BCLK) ≥ 16 MHz, or when 3.0 V < VCC1 ≤ 5.5 V and f(BCLK) ≥ 20
MHz, one wait must be inserted to read the data flash. Use the PM17 bit or the FMR17 bit to insert one
wait.
11.4.2
External Bus
When a hardware reset, power-on reset, or voltage monitor 0 reset is performed with a high-level input
on the CNVSS pin, the internal ROM cannot be read.
11.4.3
External Access Immediately after Writing to the SFRs
When accessing an external device after writing to the SFRs, the write signal and CSi signal switch
simultaneously. Thus, adjust the capacity of each signal so as not to delay the write signal.
HOLD
11.4.4
HOLD input is unavailable. Connect the HOLD pin to VCC2 via a resistor (pull-up).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
11. Bus
Page 153 of 807
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