Sampling Mode Register (Spmr); Figure 14.2 Block Diagram Of Noise Filter Circuit - Renesas H8 Series Hardware Manual

14.3.9

Sampling Mode Register (SPMR)

SPMR controls the serial communication function.
Bit Bit Name

7 to 3
2 STDSPM

1, 0
• Noise Filter Circuit
The RXD input signal is latched through the noise filter circuit. The noise filter circuit
comprises a series of three latch circuits and a match detection circuit. The RXD input signal is
sampled by the basic clock with the 16 times the transfer clock frequency. If three latch
outputs match, its level is transferred to the next stage. If not, the circuit holds the previous
value.
That is, when the incoming signal holds the same level for three clock cycles, it is regarded as
the proper signal. If the levels of the signal is less than three clock cycles, the signal is
regarded as a noise.
Sampling clock
RXD input signal
Internal basic clock cycle
Sampling clock
Initial
Value R/W

All 1
1 R/W

All 1
C C
D Q D Q
Latch Latch

Figure 14.2 Block Diagram of Noise Filter Circuit

Section 14 Serial Communication Interface 3 (SCI3)
Description
Reserved
These bits are always read as 1.
Noise Filter Function Select
Selects the noise filter function for the RXD pin in
asynchronous mode.
0: Noise filter circuit is enabled
1: Noise filter circuit is disabled
Reserved
These bits are always read as 1.
Match
C
D Q detection
Latch circuit
Rev. 3.00 Sep. 14, 2006 Page 211 of 408
Internal RXD
SPMR
signal shown
(STDSPM)
in figure 14.1
REJ09B0105-0300