Timer Mode Register (Tmdr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.2

Timer Mode Register (TMDR)

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. This
module has five TMDR registers, one each for channels 0 to 4. TMDR register settings should be changed only when
TCNT operation is stopped.
Bit Bit Name
7 —
6 BFE
5 BFB
4 BFA
3 to 0 MD[3:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6
- BFE
Initial value: 0 0
R/W: R R/W
Initial
Value R/W Description
0 R Reserved
This bit is always read as 0. The write value should always be 0.
0 R/W Buffer Operation E
Specifies whether TGRE_0 and TGRF_0 are to operate in the normal way or to
be used together for buffer operation.
TGRF compare match is generated when TGRF is used as the buffer register.
In channels 1 to 4, this bit is reserved. It is always read as 0 and the write value
should always be 0.
0: TGRE_0 and TGRF_0 operate normally
1: TGRE_0 and TGRF_0 used together for buffer operation
0 R/W Buffer Operation B
Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD
are to be used together for buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not generated in a mode other
than complementary PWM. In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB and TGRD operate normally
1: TGRB and TGRD used together for buffer operation
0 R/W Buffer Operation A
Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC
are to be used together for buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not generated in a mode other
than complementary PWM. TGRC compare match is generated when in
complementary PWM mode. When compare match for channel 4 occurs during
the Tb period in complementary PWM mode, TGFC is set. Therefore, set the
TGIEC bit in the timer interrupt enable register 4 (TIER_4) to 0.
In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as
0 and cannot be modified.
0: TGRA and TGRC operate normally
1: TGRA and TGRC used together for buffer operation
0000 R/W Modes 0 to 3
These bits are used to set the timer operating mode.
See Table 10.10 for details.
5 4 3 2 1
BFB BFA MD[3:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
10. Multi-Function Timer Pulse Unit 2
0
0
R/W
10-11