Dtc Mode Register B (Mrb) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat

area or block area, in repeat mode or block transfer mode.

Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.

DTC Mode Register B (MRB)

Initial value :

MRB is an 8-bit register that controls the DTC operating mode.

Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers

can be performed consecutively in response to a single transfer request.

In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt

source flag, and clearing of DTCER is not performed.

Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a

data transfer.

Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2357 Group, and should always be written

Destination side is repeat area or block area

Source side is repeat area or block area

Byte-size transfer

Word-size transfer

End of DTC data transfer (activation waiting state is entered)

DTC chain transfer (new register information is read, then data is transferred)

After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is

0 (the DTC clears the interrupt source flag of the activating interrupt to 0)

After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the

interrupt source flag of the activating interrupt to 0)

Rev.6.00 Oct.28.2004 page 245 of 1016

REJ09B0138-0600H